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71. 发明授权

US06392932B1 Nonvolatile memory system, semiconductor memory, and writing method 有权
公开(公告)号：US06392932B1
公开(公告)日：2002-05-21
申请号：US09714552
申请日：2000-11-17
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

72. 发明授权

US06256230B1 Nonvolatile memory device and refreshing method 有权
公开(公告)号：US06256230B1
公开(公告)日：2001-07-03
申请号：US09583949
申请日：2000-05-31
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C1134
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and programming operation performed in a short time can be realized.

73. 发明授权

US06226198B1 Nonvolatile memory device and refreshing method 有权
标题翻译：非易失性存储器件和刷新方法
公开(公告)号：US06226198B1
公开(公告)日：2001-05-01
申请号：US09472178
申请日：1999-12-27
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C1134
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and programming operation performed in a short time can be realized.
摘要翻译：在数据编程时，根据比特的组合，由数据变换逻辑电路将多个比特的数据变换为数据（多值数据），并将变换后的数据依次传送到与存储器阵列的位线。根据锁存在锁存电路中的数据产生编程脉冲，并将其应用于与多值数据对应的选择状态的存储元件。在数据读取操作中，通过将读取的电压改变为各个阈值的中间值来读出存储元件的状态，并将其传送到并存储在用于存储多值数据的寄存器中，使得原始数据可以通过基于存储在寄存器中的多值数据的数据逆变换逻辑电路来恢复。结果，可以将存储器阵列的外围电路规模抑制到相对小的尺寸，并且可以实现在短时间内执行的编程操作。

74. 发明授权

US6166949A Nonvolatile memory device and refreshing method 失效
公开(公告)号：US6166949A
公开(公告)日：2000-12-26
申请号：US106344
申请日：1998-06-29
申请人： Hitoshi Miwa
发明人： Hitoshi Miwa
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state corresponding to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and a programming operation performed in a short time can be realized.

75. 发明授权

US5867428A Nonvolatile memory system semiconductor memory and writing method 失效
标题翻译：非易失性存储器系统半导体存储器和写入方式
公开(公告)号：US5867428A
公开(公告)日：1999-02-02
申请号：US889191
申请日：1997-07-08
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C16/02 , G11C7/00 , G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
摘要翻译：非易失性半导体存储器由于与字线相关的干扰而恢复存储器单元的阈值的变化。非易失性存储器在每次写入操作之后连续执行许多写入操作，而不执行单扇区擦除，执行比通常的写入操作更快的附加写入操作，以及减轻用于附加写入的软件的负担。存储在指定扇区中的数据在保存在寄存器中之前被读出，并且当给出预定命令时，所选扇区被进行单扇区擦除。然后写入预期值数据由保存的数据和要另外编写的数据形成，完成写入操作。

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