会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 76. 发明申请
    • SHIFT REGISTER AND DISPLAY DEVICE HAVING THE SAME
    • 移位寄存器和具有该寄存器的显示器件
    • US20130100007A1
    • 2013-04-25
    • US13805769
    • 2011-04-04
    • Kaoru YamamotoYasuyuki Ogawa
    • Kaoru YamamotoYasuyuki Ogawa
    • G11C19/28G09G3/36
    • G11C19/28G09G3/36G09G3/3677G09G2310/0286G11C19/184
    • A shift register 10 is configured such that m unit circuits 11 each including a shift unit 12 and three buffer units 13r, 13g, and 13b are in a multi-stage cascade connection and that 3m signals in total including three signals from each stage are outputted. The m shift units 12 perform a shift operation, and a first signal Y is outputted from each stage. When a clock signal CK is at a high level, the first signal Y rises higher than a normal high level due to bootstrapping. The buffer unit 13r controls an output signal YR to be at a high level based on the buffer control signal CR and the first signal Y. A buffer control circuit 7 controls buffer control signals CR, CG, and CB to be at a high level for a time period shorter than a half cycle of the clock signal. With this, a shift register with a reduced circuit amount and low power consumption is provided.
    • 移位寄存器10被配置为使得包括移位单元12和三个缓冲单元13r,13g和13b的m个单元电路11处于多级级联连接,并且总共包括来自每个级的三个信号的3m信号 。 m移位单元12执行移位操作,并且从每个级输出第一信号Y. 当时钟信号CK处于高电平时,由于引导,第一信号Y比正常高电平上升。 缓冲器单元13r基于缓冲器控制信号CR和第一信号Y将输出信号YR控制在高电平。缓冲器控制电路7将缓冲器控制信号CR,CG和CB控制在高电平,以便 比时钟信号的半周期短的时间段。 由此,提供了具有降低的电路量和低功耗的移位寄存器。