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71. 发明授权

US07088156B2 Delay-locked loop having a pre-shift phase detector 有权
公开(公告)号：US07088156B2
公开(公告)日：2006-08-08
申请号：US10931354
申请日：2004-08-31
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

72. 发明申请

US20060044931A1 Delay-locked loop having a pre-shift phase detector 有权
公开(公告)号：US20060044931A1
公开(公告)日：2006-03-02
申请号：US10931354
申请日：2004-08-31
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

73. 发明授权

US06346841B2 Pulse generator 失效
标题翻译：脉冲发生器
公开(公告)号：US06346841B2
公开(公告)日：2002-02-12
申请号：US09778772
申请日：2001-02-08
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03K3017
CPC分类号： H03K5/1534
摘要： A pulse generator, which only occupies a small area in a circuit chip by using a characteristic that the potential in both ends of a capacitor is maintained. The pulse generator comprises a voltage level control unit for controlling a voltage level of a first node according to the state of input signal; a first switching unit for controlling a voltage level of a second node by performing a switching operation according to the state of the input signal; a second switching unit for changing a voltage level of the second node by performing another switching operation, opposite to the first switching means according to the state of the input signal; a charge/discharge unit for charging/discharging a voltage between the first and the second nodes according to the switching state of the first and the second switching means; and an output unit for outputting a pulse signal according to the charging/discharging state of the charge/discharge means.

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