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71. 发明授权

US06495772B2 High performance dense wire for printed circuit board 有权
标题翻译：高性能致密线用于印刷电路板
公开(公告)号：US06495772B2
公开(公告)日：2002-12-17
申请号：US09834280
申请日：2001-04-12
申请人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H05K102
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/0263 , H05K1/0265 , H05K3/4602 , H05K3/4611 , H05K2201/0352 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , H05K2203/1581 , H01L2924/00
摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.
摘要翻译：一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

72. 发明授权

US06290860B1 Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby 有权
标题翻译：在平面化薄膜电介质和由此制造的电路上设计和制造细线电路的方法
公开(公告)号：US06290860B1
公开(公告)日：2001-09-18
申请号：US09283679
申请日：1999-04-01
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

73. 发明授权

US08501575B2 Method of forming multilayer capacitors in a printed circuit substrate 有权
标题翻译：在印刷电路基板中形成多层电容器的方法
公开(公告)号：US08501575B2
公开(公告)日：2013-08-06
申请号：US12909983
申请日：2010-10-22
申请人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
IPC分类号： H01G4/00
CPC分类号： H01G4/206 , H01G4/232 , H01G4/33 , H05K1/162 , H05K3/06 , H05K3/125 , H05K3/18 , H05K2201/0187 , H05K2201/0209 , H05K2201/0257 , H05K2201/09309 , Y10T156/10
摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.
摘要翻译：在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。通道可以使用蚀刻或沉积技术进行。可光成像的电介质是层叠体的上表面。曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。然后用电容器材料填充这些空间。最后，铜层压或沉积在结构的顶部。然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

74. 发明申请

US20120223047A1 METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE 有权
标题翻译：在印刷电路基板中形成多层电容器的方法
公开(公告)号：US20120223047A1
公开(公告)日：2012-09-06
申请号：US12909983
申请日：2010-10-22
申请人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
IPC分类号： H01G4/002 , G03F7/30 , G03F7/20
CPC分类号： H01G4/206 , H01G4/232 , H01G4/33 , H05K1/162 , H05K3/06 , H05K3/125 , H05K3/18 , H05K2201/0187 , H05K2201/0209 , H05K2201/0257 , H05K2201/09309 , Y10T156/10
摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.
摘要翻译：在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。通道可以使用蚀刻或沉积技术进行。可光成像的电介质是层叠体的上表面。曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。然后用电容器材料填充这些空间。最后，铜层压或沉积在结构的顶部。然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

75. 发明申请

US20120152605A1 CIRCUITIZED SUBSTRATE WITH DIELECTRIC INTERPOSER ASSEMBLY AND METHOD 有权
标题翻译：具有介电插座组件的电路基板和方法
公开(公告)号：US20120152605A1
公开(公告)日：2012-06-21
申请号：US12972700
申请日：2010-12-20
申请人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , James J. McNamara, JR.
发明人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , James J. McNamara, JR.
IPC分类号： H05K1/11 , H05K3/36
CPC分类号： H05K3/462 , H05K1/162 , H05K1/167 , H05K3/4069 , H05K3/4602 , H05K3/4614 , H05K3/4623 , H05K2203/063 , Y10T29/49099 , Y10T29/49126 , Y10T29/49165
摘要： A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.
摘要翻译：电路基板及其制造方法，其中在电介质中介层内形成有通孔数量。基板包括两个印刷电路板（PCB）层，其结合到插入件的相对侧，每个PCB的导电特征与插入件通孔对准。电阻浆料位于邻近通孔的导电特征上，以在两个PCB的导电特征之间形成受控的电阻连接。还公开了电路化基板组件及其制造方法。

76. 发明申请

US20110017498A1 Photosensitive dielectric film 审中-公开
标题翻译：感光电介质膜
公开(公告)号：US20110017498A1
公开(公告)日：2011-01-27
申请号：US12460975
申请日：2009-07-27
申请人： John M. Lauffer , Voya R. Markovich , Kostas I. Papathomas
发明人： John M. Lauffer , Voya R. Markovich , Kostas I. Papathomas
IPC分类号： H05K1/09 , C08J3/28 , B05D5/12
CPC分类号： H05K3/4676 , H05K3/0023 , H05K2201/0209
摘要： A photosensitive dielectric composition adapted for forming a dielectric film layer for use in a circuitized substrate is provided according to one embodiment of the invention, the composition including an epoxide bearing component including at least one polyepoxide resin curable by electromagnetic radiation, a cyanate ester, a flexibilizer, a nanostructured toughener, a photoinitiator in a predetermined amount by weight of the resin component, and a ceramic filler, the photosensitive dielectric composition forming the dielectric film layer having no solvent therein. In an alternative embodiment, a heat activated dielectric composition is provided which is curable by heat and includes an epoxide bearing component including at least one polyepoxide resin curable by heat, a cyanate ester, a flexibilizer, a nanostructured toughener, a heat activated curing agent for accelerating reaction of the cyanate ester and polyepoxide resin components, and a ceramic filler. Methods of making circuitized substrates from the above compositions are also provided.
摘要翻译：根据本发明的一个实施方案提供一种适用于形成用于电路化基底的电介质膜层的光敏电介质组合物，该组合物包括含环氧化物的组分，该组分包括至少一种可通过电磁辐射固化的聚环氧树脂，氰酸酯，增韧剂，纳米结构增韧剂，预定量的树脂组分的光引发剂和陶瓷填料，所述光敏介电组合物形成在其中不溶剂的电介质膜层。在另一个实施方案中，提供热活化电介质组合物，其可通过加热固化，并且包括含环氧化物的组分，其包含至少一种可热固化的聚环氧树脂，氰酸酯，增韧剂，纳米结构增韧剂，热活化固化剂加速氰酸酯和聚环氧树脂组分的反应，以及陶瓷填料。还提供了从上述组合物制备电路化基底的方法。

77. 发明授权

US07491896B2 Information handling system utilizing circuitized substrate with split conductive layer 有权
标题翻译：信息处理系统利用具有分裂导电层的电路化基板
公开(公告)号：US07491896B2
公开(公告)日：2009-02-17
申请号：US12010004
申请日：2008-01-18
申请人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
发明人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
IPC分类号： H05K1/11
CPC分类号： H01L23/49811 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H05K1/0216 , H05K1/0256 , H05K1/056 , H05K3/0047 , H05K3/429 , H05K3/44 , H05K3/4641 , H05K2201/093 , H05K2201/09345 , H05K2201/09481 , H05K2201/09663 , H05K2201/0969 , H05K2203/0323 , H05K2203/1476 , Y10T29/49126 , Y10T29/49155 , Y10T29/49162 , Y10T29/49165 , Y10T29/49176 , H01L2224/0401
摘要： An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.
摘要翻译：一种信息处理系统，例如主机计算机，其包括作为其一部分的壳体，其中具有包括电路化基板的电组件，该电组件又包括多个邻接的开放段，其限定导电层内的相对边缘部分，以隔离单独的导电层的部分，使得该层可用于不同的功能，例如作为系统内的功率和接地元件。至少一个电气部件位于系统的电气组件的电路化基板上并电耦合到电路基板。

78. 发明申请

US20080248596A1 Method of making a circuitized substrate having at least one capacitor therein 审中-公开
标题翻译：制造其中具有至少一个电容器的电路化基板的方法
公开(公告)号：US20080248596A1
公开(公告)日：2008-10-09
申请号：US11878673
申请日：2007-07-26
申请人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , How T. Lin , John M. Lauffer , Voya R. Markovich
IPC分类号： H01L21/77
CPC分类号： H01G4/206 , H01G4/232 , H01G4/33 , H05K1/162 , H05K3/0032 , H05K3/107 , H05K2201/0209 , H05K2201/0257 , H05K2201/09236 , H05K2201/09309 , H05K2201/09881 , H05K2203/0108 , H05K2203/066
摘要： A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.
摘要翻译：一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。然后在电容器顶部形成第二电介质层，并产生电容器“芯”。然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。在另一个实施例中，可以在沉积在电介质层上的金属层内形成至少两个间隔开的导体，这些导体在其间限定通道。然后可以在通道内沉积（例如，使用层压）的电容电介质材料。

79. 发明授权

US07326643B2 Method of making circuitized substrate with internal organic memory device 失效
标题翻译：制造具有内部有机存储器件的电路化衬底的方法
公开(公告)号：US07326643B2
公开(公告)日：2008-02-05
申请号：US11808596
申请日：2007-06-12
申请人： Subahu D. Desai , How T. Lin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Subahu D. Desai , How T. Lin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H01L21/4751
CPC分类号： G11C11/22 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/16 , H05K2201/0166 , H05K2201/0179 , H05K2201/09763 , H05K2201/10159 , H01L2224/0401
摘要： A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.
摘要翻译：一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成设备。

80. 发明授权

US07253502B2 Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same 失效
标题翻译：具有内部有机存储器件的电路化衬底，利用其的电气组件以及利用其的信息处理系统
公开(公告)号：US07253502B2
公开(公告)日：2007-08-07
申请号：US10900385
申请日：2004-07-28
申请人： Subahu D. Desai , How T. Lin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Subahu D. Desai , How T. Lin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H01L23/58
CPC分类号： G11C11/22 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/16 , H05K2201/0166 , H05K2201/0179 , H05K2201/09763 , H05K2201/10159 , H01L2224/0401
摘要： A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.
摘要翻译：一种电路化衬底，由至少一层具有导电图案的电介质材料构成。图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成设备。衬底优选地与其它介电电路分层组件组合以形成多层衬底，在多层衬底上，可以将耦合到内部存储器件的分立电子部件（例如，逻辑芯片）放置在其上以与之组合工作。还提供了能够使用基板的电气组件，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

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