会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 73. 发明申请
    • Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
    • 在微处理器系统访问存储器件时检测和纠正错误的方法和系统
    • US20050283650A1
    • 2005-12-22
    • US10919138
    • 2004-08-16
    • Yan ZhangPaul LuYue Chen
    • Yan ZhangPaul LuYue Chen
    • G06F11/00
    • G06F11/1008G06F11/1076
    • A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error correction code generation, and receiving a first indication of the specified device, a second indication of the data, and a third indication of a size of the data during the monitoring. A new error correction code may be generated in hardware for the data based on the indicated size of the data and an indication may be provided to signal when generation of the new error correction code for a specified number of accesses for at least a portion of the data is complete. Detected errors may be corrected in software based on the newly generated error correction code. The first indication may be a device selection signal and the error correction code generation may be enabled or disabled via an enable signal.
    • 一种用于确保数据处理系统中的数据完整性的方法和系统可以包括监视指定设备的数据是否可用于产生纠错码,以及接收指定设备的第一指示,数据的第二指示,以及第三 在监视期间指示数据的大小。 可以基于所指示的数据大小在数据的硬件中生成新的纠错码,并且可以提供指示,用于当针对至少一部分的数据的指定数量的访问生成新的纠错码时, 数据完成。 检测到的错误可能会根据新生成的纠错码在软件中进行修正。 第一指示可以是设备选择信号,并且可以经由使能信号使能或禁用纠错码生成。
    • 74. 发明申请
    • Method and system for codec with polyringer
    • 多音节编解码器的方法和系统
    • US20050278044A1
    • 2005-12-15
    • US10926762
    • 2004-08-26
    • Yue ChenMinsheng Wang
    • Yue ChenMinsheng Wang
    • G06F17/00G10H7/00
    • G10H7/004G10H2230/021G10H2250/631
    • In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma demodulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.
    • 在一种音频处理装置中,提供了一种用于改进具有多声道的CODER的方法和系统。 音频CODEC可以包括音频ADC,音频DAC和侧音发生器。 来自外部麦克风的数据可以由音频ADC处理,并且可以被发送到可适于执行数字信号处理操作的处理器。 音频DAC可以从处理器接收数字音频和复音振铃器数据,并且可以通过单独的数字滤波器和数字内插器处理数字音频和复音振铃器数据。 音频DAC可以在模拟转换之前添加经处理的数字音频和复音振铃器数据。 音频DAC可以通过利用Δ-Σ解调器,基于电流的DAC和开关电容滤波器来执行模拟转换。 转换的数据可以用RC滤波器滤波,并且可以用于驱动外部扬声器或听筒。
    • 77. 发明授权
    • High current and/or high speed electrically erasable memory cell for programmable logic devices
    • 用于可编程逻辑器件的高电流和/或高速电可擦除存储单元
    • US06525962B1
    • 2003-02-25
    • US09543462
    • 2000-04-05
    • Sheng-Yueh PaiYue ChenKevin Yen
    • Sheng-Yueh PaiYue ChenKevin Yen
    • G11C1606
    • H01L27/115G11C16/0441H01L27/0207H01L27/11803
    • An electrically erasable programmable logic device (EEPLD) cell (100) is disclosed. A folded floating gate (110) and folded select gate (108) can form two parallel read current paths (Isense0 and Isense1). A first read current path (Isense0) may be formed between a first semiconductor region (104) and a second semiconductor region (106-0), and may be controlled by a first floating gate portion (110-0) and a first select gate portion (108-0). A second read current path (Isense1) may be formed between the first semiconductor region (104) and a third semiconductor region (106-1) that is coupled to a second semiconductor region (106-0). A second read current path (Isense1) may be controlled by a second floating gate portion (110-1) and a second select gate portion (108-1).
    • 公开了一种电可擦除可编程逻辑器件(EEPLD)单元(100)。 折叠浮动门(110)和折叠选择门(108)可以形成两个并行读取电流路径(Isense0和Isense1)。 可以在第一半导体区域(104)和第二半导体区域(106-0)之间形成第一读取电流路径(Isense0),并且可以由第一浮动栅极部分(110-0)和第一选择栅极 部分(108-0)。 可以在第一半导体区域(104)和耦合到第二半导体区域(106-0)的第三半导体区域(106-1)之间形成第二读取电流路径(Isense1)。 第二读取电流路径(Isense1)可以由第二浮动栅极部分(110-1)和第二选择栅极部分(108-1)来控制。