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    • 73. 发明授权
    • Transistors including laterally extended active regions and methods of fabricating the same
    • 包括横向延伸的有源区的晶体管及其制造方法
    • US07470588B2
    • 2008-12-30
    • US11387029
    • 2006-03-22
    • Min-Hee ChoJi-Young Kim
    • Min-Hee ChoJi-Young Kim
    • H01L21/336
    • H01L29/66621H01L21/823481H01L27/10876H01L29/78
    • A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.
    • 晶体管包括衬底和设置在衬底中的隔离区。 隔离区域限定包括上部和下部有源区域的有源区域,上部有源区域具有第一宽度,而下部有源区域具有大于第一宽度的第二宽度。 绝缘栅电极延伸穿过上有源区并进入下有源区。 源极和漏极区域设置在绝缘栅电极的相应第一和第二侧上的有源区中。 绝缘栅电极可以包括设置在上有源区中的上栅电极和设置在下有源区中的下栅电极,其中下栅电极比上栅极电极宽。 描述相关的制造方法。
    • 74. 发明申请
    • Method and apparatus for allocating channel quality information channel in a wireless communication system
    • 在无线通信系统中分配信道质量信息信道的方法和装置
    • US20070155392A1
    • 2007-07-05
    • US11649183
    • 2007-01-03
    • Min-Hee ChoHee-Kwun ChoHyeong-Jong Ju
    • Min-Hee ChoHee-Kwun ChoHyeong-Jong Ju
    • H04Q7/20
    • H04W72/10
    • A method and apparatus for dynamically allocating and releasing a Channel Quality Information CHannel (CQICH) to and from a Mobile Station (MS) in a Base Station (BS) communicating with a plurality of MSs on a common radio channel in a wireless communication system are provided, in which the BS determines whether the MS is under a first group, when a CQICH is to be allocated to the MS, determines whether any data transmission has occurred for a CQICH allocation period preset for the first group and counted from a reallocation time, if the MS is under the first group, and groups the MS to a second group and reallocates a CQICH to the MS, the second group having a lower priority level than the first group, if no data transmission has occurred for the CQICH allocation period.
    • 一种用于在无线通信系统中的公共无线电信道上与多个MS通信的基站(BS)中的移动站(MS)动态分配和释放信道质量信息信道(CQICH)的方法和装置, 其中BS确定MS是否在第一组之下,当CQICH将被分配给MS时,确定是否针对第一组预设的CQICH分配周期发生了任何数据传输并从重新分配时间计数 如果MS处于第一组之下,并且将MS分组到第二组并且将重新分配给MS的CQICH,则如果没有针对CQICH分配周期发生数据传输,则第二组具有比第一组更低的优先级 。
    • 77. 发明授权
    • Recessed gate transistor structure and method of forming the same
    • 嵌入式晶体管结构及其形成方法
    • US07153745B2
    • 2006-12-26
    • US10963928
    • 2004-10-12
    • Min-Hee ChoJi-Young Kim
    • Min-Hee ChoJi-Young Kim
    • H01L21/336
    • H01L29/66621H01L29/41758H01L29/4238H01L29/66659H01L29/7834
    • Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.
    • 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准,也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层,然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后,形成源/漏区。