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    • 71. 发明申请
    • MEMORY WITH INCREASED WRITE MARGIN BITCELLS
    • 存储器增加写入字节位数
    • US20080117666A1
    • 2008-05-22
    • US11561255
    • 2006-11-17
    • Andrew C. RussellPrashant U. KenkarePerry H. Pelley
    • Andrew C. RussellPrashant U. KenkarePerry H. Pelley
    • G11C11/00
    • G11C11/412G11C8/16
    • A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
    • 一种存储器,包括第一位线,第二位线,字线,具有第一输入/输出节点和第二输入/输出节点的第一对交叉耦合的反相器,第一电源节点和第二电源 节点,其中所述第一电源节点耦合到第一电源端子。 存储器还包括耦合在第二电源端子和第二电源节点之间的第一门控晶体管,第一门控晶体管在第一对写入期间接收将门控晶体管栅极到非导通状态的第一写使能信号 的交叉耦合逆变器。 存储器还包括耦合到第一字线,第一输入/输出节点和第一位线的第一传输晶体管和耦合到第一字线的第二传输晶体管,第二输入/输出节点和第二位 线。
    • 72. 发明申请
    • CONTROLLED RELIABILITY IN AN INTEGRATED CIRCUIT
    • 集成电路中控制的可靠性
    • US20080091990A1
    • 2008-04-17
    • US11536342
    • 2006-09-28
    • Klas M. BruceAndrew C. RussellShayan ZhangBradford L. Hunter
    • Klas M. BruceAndrew C. RussellShayan ZhangBradford L. Hunter
    • G11C29/00
    • G11C29/42G11C5/147G11C29/02G11C29/021G11C29/028
    • Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.
    • 提供了用于配置与包括可寻址单元的存储器阵列的至少一部分相关联的特性的方法和系统。 一方面,一种用于控制存储器阵列的电源电压的方法包括使用耦合到存储器阵列的第一电源电压来检测在对存储器阵列的可寻址单元执行读取操作时是否发生错误。 该方法还包括增加误差计数器以跟踪与存储器阵列相关联的误差计数,并且如果误差计数等于或超过存储器阵列的误差阈值,则将存储器阵列切换到第二电源电压。 该方法还包括基于至少一个条件,将存储器阵列切换到第一电源电压并将错误计数器重置为初始值。