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71. 发明申请

US20110169082A1 METHOD FOR FORMING RETROGRADED WELL FOR MOSFET 有权
标题翻译：用于形成MOSFET的退火方法
公开(公告)号：US20110169082A1
公开(公告)日：2011-07-14
申请号：US12687287
申请日：2010-01-14
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/84 , H01L27/12 , H01L29/1083 , H01L2221/6835 , H01L2221/68368
摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.
摘要翻译：提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。形成接触至少一个半导体器件和第一半导体层的处理结构。去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含的回归井掺杂剂。退火井可以进行激光退火。

72. 发明申请

US20110059587A1 DEVICE HAVING SELF-ALIGNED DOUBLE GATE FORMED BY BACKSIDE ENGINEERING, AND DEVICE HAVING SUPER-STEEP RETROGRADED ISLAND 有权
标题翻译：具有由背面工程形成的自对准双门的装置，以及具有超级退化岛的装置
公开(公告)号：US20110059587A1
公开(公告)日：2011-03-10
申请号：US12556604
申请日：2009-09-10
申请人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66484 , H01L29/6659 , H01L29/66636 , H01L29/66742 , H01L29/7831 , H01L29/78648
摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.
摘要翻译：提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。在衬底的暴露部分上形成外延半导体材料。去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。还提供了形成退火岛的方法。

73. 发明授权

US09054221B2 Semiconductor device with a common back gate isolation region and method for manufacturing the same 有权
标题翻译：具有公共背栅隔离区的半导体器件及其制造方法
公开(公告)号：US09054221B2
公开(公告)日：2015-06-09
申请号：US13510807
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/336 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

74. 发明授权

US08952453B2 MOSFET formed on an SOI wafer with a back gate 有权
标题翻译：在具有背栅的SOI晶片上形成MOSFET
公开(公告)号：US08952453B2
公开(公告)日：2015-02-10
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

75. 发明授权

US08658507B2 MOSFET structure and method of fabricating the same using replacement channel layer 有权
标题翻译： MOSFET结构及其制造方法采用替代沟道层
公开(公告)号：US08658507B2
公开(公告)日：2014-02-25
申请号：US12990714
申请日：2010-06-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： There is provided a MOSFET structure and a method of fabricating the same. The method includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.
摘要翻译：提供了一种MOSFET结构及其制造方法。该方法包括：提供半导体衬底; 在半导体衬底上形成虚拟栅极; 形成源/漏区; 选择性地将伪栅极蚀刻到要形成沟道的位置; 并且在通道的位置上外延生长沟道层，并在沟道层上形成栅极，其中沟道层包括高迁移率的材料。因此，在形成源极/漏极区域之后，器件的沟道被高迁移率的材料代替，从而可以抑制短沟道效应并且还能够提高器件性能。

76. 发明授权

US08441045B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08441045B2
公开(公告)日：2013-05-14
申请号：US13378206
申请日：2011-02-27
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/085 , H01L29/84 , H01L29/80 , H01L31/112 , H01L29/04
CPC分类号： H01L29/165 , H01L21/30608 , H01L29/1054 , H01L29/1083 , H01L29/517 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要翻译：本申请公开了一种半导体器件及其制造方法。其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称基质。本发明的实施例可应用于半导体器件制造中的应力工程技术。

77. 发明授权

US08426920B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US08426920B2
公开(公告)日：2013-04-23
申请号：US13379111
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12
CPC分类号： H01L29/78648
摘要： The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.
摘要翻译：本申请提供了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 半导体衬底上的第一掩埋绝缘层; 形成在第一掩埋绝缘层上的第一半导体层中的背栅; 在所述第一半导体层上的第二掩埋绝缘层; 源极/漏极区，形成在第二绝缘层上的第二半导体层中; 第二半导体层上的栅极; 以及源极/漏极区域，栅极和背栅极之间的电接触，其中后栅极仅在沟道区域和源极/漏极区域中的一个并且不在源极/漏极区域的另一个之下，并且具有公共在后栅极和源极/漏极区域之间形成电接触。 MOSFET改善了通过不对称背栅抑制短沟道效应的效果，并且通过使用公共导电通孔来减小晶片上的占位面积。

78. 发明申请

US20130093020A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130093020A1
公开(公告)日：2013-04-18
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一虚拟栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

79. 发明申请

US20130093002A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130093002A1
公开(公告)日：2013-04-18
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78648 , H01L21/2652 , H01L21/2658 , H01L21/74 , H01L29/66545 , H01L29/66772
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体衬底，所述半导体衬底上的埋入绝缘层以及所述埋入绝缘层上的半导体层; 半导体层上的栅叠层; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 以及位于所述源极区域和所述漏极区域之间的所述半导体层中的沟道区域，其中，所述MOSFET还包括位于所述半导体衬底中并具有作为所述后栅极的下部的第一掺杂区域的背栅极和第二掺杂区域作为背栅极的上部，并且后栅极的第二掺杂区域与栅极堆叠自对准。 MOSFET可以通过改变背栅的掺杂类型和掺杂浓度来调节阈值电压。

80. 发明申请

US20130069041A1 METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：制造石墨纳米薄膜的方法，MOSFET及其制造方法
公开(公告)号：US20130069041A1
公开(公告)日：2013-03-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/20 , H01L21/336 , H01L29/775 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

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