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    • 71. 发明申请
    • DIFFERENTIALLY PROCESSED TISSUE AND PROCESSING METHODS THEREOF
    • 不同加工组织及其加工方法
    • US20080294270A1
    • 2008-11-27
    • US11753102
    • 2007-05-24
    • Jian Q. YaoHai-Qing XianJizong GaoRodney BristolVictor ZaporojanHali WangHui Liu
    • Jian Q. YaoHai-Qing XianJizong GaoRodney BristolVictor ZaporojanHali WangHui Liu
    • A61L27/38A61F2/28D01C3/00
    • A61L27/3608A61L27/3604A61L27/3683
    • A method of preparing an implantable biological device having a first tissue part and a second tissue part includes exposing the first tissue part to a first preparation method and preventing exposure of the second biological tissue part to the first preparation method. Preventing exposure of the second biological tissue part to the first preparation method may be achieved using an embedding technique, a coating technique, a covering technique, or physical isolation. The method may further include exposing the second tissue part to a second preparation method and preventing exposure of the first biological tissue part to the second preparation method. An apparatus for preparing an implantable biologic device includes an enclosure having first and second chambers separated by a partition member wherein a substantial portion of the first tissue part is within the first chamber and a substantial portion of the second tissue part is within the second chamber.
    • 制备具有第一组织部分和第二组织部分的可植入生物装置的方法包括将第一组织部分暴露于第一制备方法并防止第二生物组织部分暴露于第一制备方法。 可以使用嵌入技术,涂覆技术,覆盖技术或物理隔离来防止第二生物组织部分暴露于第一制备方法。 该方法可以进一步包括将第二组织部分暴露于第二制备方法并防止第一生物组织部分暴露于第二制备方法。 一种用于制备可植入生物装置的装置,包括具有由分隔构件分开的第一和第二腔室的外壳,其中所述第一组织部分的大部分位于所述第一腔室内,并且所述第二组织部分的大部分位于所述第二腔室内。
    • 74. 发明授权
    • Programmable logic device with power supply noise monitoring
    • 可编程逻辑器件,具有电源噪声监测功能
    • US07359811B1
    • 2008-04-15
    • US11153984
    • 2005-06-16
    • Hui Liu
    • Hui Liu
    • G05F1/40
    • G06F17/5054
    • Programmable logic device power supply noise levels are characterized using internal measurements. By making power supply noise measurements internally, noise measurements are made without influence from device packaging or circuit board environmental effects. The input-output circuitry of a programmable logic device is configured to supply a power supply voltage from the output of an output buffer to one of the inputs of a differential input buffer. The other of the inputs of the differential input buffer is provided with a reference voltage from an external voltage reference circuit. The differential input buffer serves as a comparator and generates an output signal based on a comparison of the power supply voltage from the output buffer and the reference voltage. A noise monitoring circuit processes the output of the input buffer. The noise monitoring circuit may be based on a register.
    • 可编程逻辑器件电源噪声电平采用内部测量表征。 通过内部进行电源噪声测量,噪声测量不受设备封装或电路板环境影响的影响。 可编程逻辑器件的输入输出电路被配置为将电源电压从输出缓冲器的输出提供给差分输入缓冲器的输入之一。 差分输入缓冲器的另一个输入端提供有来自外部参考电路的参考电压。 差分输入缓冲器用作比较器,并且基于来自输出缓冲器的电源电压与参考电压的比较来产生输出信号。 噪声监测电路处理输入缓冲器的输出。 噪声监测电路可以基于寄存器。
    • 75. 发明授权
    • Method and system for improving memory interface data integrity
    • 提高内存接口数据完整性的方法和系统
    • US07352299B1
    • 2008-04-01
    • US11560673
    • 2006-11-16
    • Hui Liu
    • Hui Liu
    • H03M7/00
    • G06F11/1032
    • An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder sets a status bit to indicate that the data are encoded. The encoder includes two encoding stages to further enhance the data integrity and transfer. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, including the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data. The decoder is connected in series with the parity checker.
    • 提供了一种用于优化到外部存储器接口总线的数据呈现的集成电路(IC)。 IC通过外部存储器接口总线与外部存储器通信。 该IC包括编码器,其可以对正在发送到外部存储器的数据进行编码。 编码器根据数据中大多数位的逻辑值对数据进行编码。 编码器设置状态位以指示数据被编码。 编码器包括两个编码级,以进一步增强数据的完整性和传输。 进一步与编码器串联的是奇偶校验发生器,其基于包括状态位在内的数据中的逻辑1的数量是偶数还是奇数来设置奇偶校验位逻辑值。 IC还包括一个奇偶校验器,用于检测在传输过程中数据是否发生错误。 IC内的解码器将数据解码为原始数据。 解码器与奇偶校验器串联连接。
    • 79. 发明申请
    • SYSTEM FOR IMPROVING MEMORY INTERFACE DATA INTEGRITY IN PLDS
    • 改进PLDS中记忆界面数据完整性的系统
    • US20060290542A1
    • 2006-12-28
    • US11458962
    • 2006-07-20
    • Hui Liu
    • Hui Liu
    • H03M7/34
    • G06F11/1032
    • An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.
    • 提供了一种用于优化到外部存储器接口总线的数据呈现的集成电路(IC)。 IC通过外部存储器接口总线与外部存储器通信。 该IC包括编码器,其可以对正在发送到外部存储器的数据进行编码。 编码器根据数据中大多数位的逻辑值对数据进行编码。 编码器能够设置状态位以指示数据被编码。 进一步与编码器串联的是奇偶校验发生器,其基于数据中的逻辑1的数量以及状态位是偶数还是奇数来设置奇偶校验位逻辑值。 IC还包括一个奇偶校验器,用于检测在传输过程中数据是否发生错误。 IC内的解码器将数据解码为原始数据。