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71. 发明专利

JPS60167462A SOLID-STATE IMAGE PICKUP DEVICE 失效
公开(公告)号：JPS60167462A
公开(公告)日：1985-08-30
申请号：JP2168184
申请日：1984-02-10
申请人： HITACHI LTD
发明人： NAKAI MASAAKI , OOBA SHINYA , ANDOU HARUHISA , OZAKI TOSHIBUMI , ONO HIDEYUKI , OZAWA NAOKI , TAKEMOTO KAYAO
IPC分类号： H01L27/146 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/372 , H04N5/374
摘要： PURPOSE:To enable marked reduction in blooming or vertical smear by accumulating three of the charge of only dummy signals and the charge of picture element signals in a CTD by a method wherein, using a four-phase CTD, dummy signals are cancelled by means of an external subtractor. CONSTITUTION:The titled device is constructed so as to read only dummy signal charge in the CTD18, and to reduce the dummy signals mixed in the signal charges by making differences outside. To realize this, the CTD18 is driven in four phases so as to accumulate and transfer three kinds of charges. This CTD18 is used for impressing a pulse of four-phase pulses phi1-phi4 by using every connection of the first electrode 41 and the second electrode 42 as a pair. Each pulse of the four phases generates at the same period without duplication; therefore, the charges are transferred through the CTD18 by the successive transfer of low potential positions. When the CTD18 is driven in four phases, information can be accumulated to parts corresponding to three phases of the four phases.

72. 发明专利

JP2001036818A CCD-TYPE SOLID-STATE IMAGE PICKUP ELEMENT 失效
公开(公告)号：JP2001036818A
公开(公告)日：2001-02-09
申请号：JP2000176189
申请日：2000-06-12
申请人： HITACHI LTD
发明人： OZAKI TOSHIBUMI , NAKAI MASAAKI , TANAKA HARUHIKO , ONO HIDEYUKI , SATO AKIRA
IPC分类号： H01L27/148 , H04N5/335 , H04N5/341 , H04N5/357 , H04N5/369 , H04N5/3725 , H04N5/3728 , H04N5/376 , H04N5/378
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption of an output circuit by providing a horizontal CCD transfer pulse generation circuit which inputs a trigger pulse to generate a pulse being negative in its lowest voltage and to apply the pulse to a horizontal CCD. SOLUTION: This element is provided with a horizontal CCD transfer pulse generation circuit 14 which inputs a trigger pulse to generate a pulse being negative in its lowest voltage and to apply this negative voltage pulse to the electrode of a horizontal CCD 3. Then, the circuit 14 generates a negative voltage pulse having restricted voltage amplitude from a negative power source value pulse by the input of the trigger pulse to apply to the CCD 3. By this constitution, an external driver is unnecessitated by a CCD-type image pickup element, the number of power sources for supplying to an external DC-DC converter is reduced and adjustment of DC voltage to apply to a substrate is unnecessitated at the time of preparing a camera system, thereby handleability is improved. The power consumption of a camera is reduced by unnecessitating the driver to provide outside of the element.

73. 发明专利

JPH1083996A MANUFACTURING METHOD OF FIELD-EFFECT COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1083996A
公开(公告)日：1998-03-31
申请号：JP23752496
申请日：1996-09-09
申请人： HITACHI LTD
发明人： ICHIKAWA HIROICHI , MORI MITSUHIRO , UMEMOTO YASUNARI , ONO HIDEYUKI
IPC分类号： H01L29/812 , H01L21/338
摘要： PROBLEM TO BE SOLVED: To decrease the temperature change of a threshold voltage with a source resistance being decreased, by setting the substrate temperature and the atmospheric temperature around the substrate in the processes after a gate electrode is attached, so as not to exceed the substrate temperature when the gate electrode is attached. SOLUTION: A gate electrode 2 is attached in the direction in parallel with the direction of 01-1} on the surface 100} of a 3-5 compound semiconductor 1. In each process from the attachment of the gate electrode 2 to the liftoff for forming the gate electrode 2, the substrate temperature and the atmospheric temperature around the substrate are set at the room temperature. Then, the substrate temperature at coating SiO2 of an insulating film 5 is also set at the room temperature not to exceed the substrate temperature when the gate electrode 2 is attached. Thus, the volume of the gate electrode 2 is not decreased, the inner stress of tensile property is not generated in the electrode 2 and the temperature change of a threshold voltage can be decreased with a source resistance being decreased.

74. 发明专利

JPH0745637A COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0745637A
公开(公告)日：1995-02-14
申请号：JP18784593
申请日：1993-07-29
申请人： HITACHI LTD
发明人： ONO HIDEYUKI , MORI MITSUHIRO
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/812
摘要： PURPOSE:To accurately form an offset gate structure by providing an insulating film having a prescribed shape on a semiconductor substrate and deciding the difference between a source- and drain-side recessing lengths of the substrate based on the side etching amount of the insulating film. CONSTITUTION:An insulating film 3 having a prescribed shape is formed on an epitaxial semiconductor substrate 1 and the difference between the source- and drain-side recessing length of the substrate 1 is decided based on the side etching amount of the film 3. For example, a silicon oxide film 2 and silicon nitride film 3 are grown on a GaAs substrate 1 and, after a desired pattern 4 is formed by patterning a photoresist film formed on the film 3, the film 3 is dry-etched. Then, after growing another oxide film 5 and coating the film 5 with another photoresist film 6, a gate opening 7 is formed and the oxide films 2 and 5 and nitride film 3 are dry-etched. Thereafter, a recessed area 9 is formed by etching off the substrate by a required amount after side etching the film 3 by a required amount and removing the oxide film 2 from an opening 8.

75. 发明专利

JPH0682824B2 失效
公开(公告)号：JPH0682824B2
公开(公告)日：1994-10-19
申请号：JP26610484
申请日：1984-12-19
申请人： HITACHI LTD
发明人： KOIKE NORIO , NAKAI MASAAKI , ANDO HARUHISA , OZAKI TOSHIBUMI , OOBA SHINYA , ONO HIDEYUKI
IPC分类号： H01L27/14 , H01L27/148 , H04N5/335 , H04N5/341 , H04N5/372

76. 发明专利

JPH0618266B2 失效
公开(公告)号：JPH0618266B2
公开(公告)日：1994-03-09
申请号：JP24811684
申请日：1984-11-26
申请人： HITACHI LTD
发明人： KOIKE NORIO , NAKAI MASAAKI , ONO HIDEYUKI , OOBA SHINYA , ANDO HARUHISA , OZAKI TOSHIBUMI
IPC分类号： H01L27/14 , H01L27/146 , H01L27/148 , H04N5/335 , H04N5/341 , H04N5/3728

77. 发明专利

JPH0618265B2 失效
公开(公告)号：JPH0618265B2
公开(公告)日：1994-03-09
申请号：JP8768484
申请日：1984-05-02
申请人： HITACHI LTD
发明人： NAKAI MASAAKI , KOIKE NORIO , ONO HIDEYUKI , OOBA SHINYA , ANDO HARUHISA , OZAKI TOSHIBUMI , TAKEMOTO KAYAO
IPC分类号： H01L27/14 , H01L27/148 , H04N5/335 , H04N5/365 , H04N5/3728

78. 发明专利

JPH05190825A SOLID-STATE IMAGE-SENSING ELEMENT 失效
公开(公告)号：JPH05190825A
公开(公告)日：1993-07-30
申请号：JP275392
申请日：1992-01-10
申请人： HITACHI LTD
发明人： SATO AKIRA , NAKAI MASAAKI , OZAKI TOSHIBUMI , ONO HIDEYUKI , TANAKA HARUHIKO
IPC分类号： H01L27/146 , H01L31/10 , H04N5/335 , H04N5/359 , H04N5/361 , H04N5/369 , H04N5/372 , H04N5/374 , H04N5/378
摘要： PURPOSE:To obtain a solid-state image-sensing element which prevents sensitivity from dropping and permits easy read-out of electric charge by making a highly concentrated p-type diffusion layer of a photo diode surface shallow. CONSTITUTION:A p-well diffusion layer 2, a gate oxide film 3, a gate electrode 4 and a photo diode n-type diffusion layer 6 are formed, and the gate oxide film 3 on a photo diode is removed by means of dry etching or wet etching with an interlayer oxide film 5 on the gate electrode used as a mask. Then a doped silicon film with boron B doped or a silicon oxide film 8 is deposited, and a p-type diffusion layer 7 is formed by means of thermal treatment at 950 deg.C or lower or by means of diffusion by momentary annealing at 1200 deg.C or lower or by laser annealing. Therefore a crystal defect is not likely to occur due to ion implantation damage, so that the highly concentrated p-type diffusion layer of 10 atms/cm or higher can be formed shallowly at 0.1mum or less, allowing a solid-state image-sensing element to be obtained, which can suppress dark current.

79. 发明专利

JPH04186980A CHARGE TRANSFER TYPE SOLID-STATE IMAGE PICKUP ELEMENT 失效
公开(公告)号：JPH04186980A
公开(公告)日：1992-07-03
申请号：JP31398790
申请日：1990-11-21
申请人： HITACHI LTD
发明人： ONO HIDEYUKI , NAKAI MASAAKI
IPC分类号： H01L27/148 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/355 , H04N5/359 , H04N5/361 , H04N5/369 , H04N5/3722
摘要： PURPOSE:To set a low level of an applied voltage to such a voltage that a hole is accumulated under a vertical CCD gate, and to reduce a dark current mixed into a signal charge by executing pulse driving to a vertical CCD gate electrode so as not to execute substantially a transfer in other period than vertical blanking. CONSTITUTION:A vertical CCD gate electrode is subjected to pulse driving at every horizontal blanking period (for instance, a period 45) in other period than vertical blanking. As a result, a low level of a vertical CCD gate voltage can be set such a sufficiently low voltage that a hole is accumulated under a gate, therefore, a dark current of a vertical CCD part can be set to a sufficiently small value. By taking a driving waveform of a vertical CCD as shown in the figure (a), a signal charge is transferred as shown in the figure (b), and the vertical CCD gate electrode can be subjected to pulse driving so that the transfer is not executed substantially.

80. 发明专利

JPH0499381A SOLID-STATE IMAGE SENSOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0499381A
公开(公告)日：1992-03-31
申请号：JP21755690
申请日：1990-08-17
申请人： HITACHI LTD
发明人： ONO HIDEYUKI , TANAKA HARUHIKO , OZAKI TOSHIBUMI , SATO AKIRA , NAKAI MASAAKI
IPC分类号： H01L27/148 , H04N5/335 , H04N5/341 , H04N5/359 , H04N5/361 , H04N5/369 , H04N5/372
摘要： PURPOSE:To simplify a gate electrode forming process by forming a transfer gate electrode of the same layer as a gate electrode for forming a horizontal shift register or transferring between the horizontal shift registers by punchthrough to eliminate the transfer gate electrode. CONSTITUTION:Patterns of gate electrodes 11, 13 of a vertical shift register, a first gate electrode 14 of a first horizontal shift register, and a transfer gate electrode 22 are formed in a photoetching step. After oxide films 186-189 are formed on the electrodes 11, 13, 14, 22 by wet oxidizing, a second layer polycrystalline silicon film is deposited, and patterns of a gate electrode 12 of a vertical shift register, a second gate electrode 23 of the first horizontal shift register and a second gate electrode 25' of a second horizontal shift register are formed. Then, after an SiO2 film 183 is deposited a contact hole is formed on the electrode 14. After Al films 16, 17 are deposited, they are used as the gate wirings of the horizontal shift register.

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