专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20110300703A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110300703A1
公开(公告)日：2011-12-08
申请号：US13211394
申请日：2011-08-17
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向形成在半导体衬底上的多个隧道绝缘膜，和在每个方向上具有一定间隔的与第一方向正交的第二方向，多个电荷累积层形成在多个分别形成在所述半导体衬底上的多个元件隔离区域，所述多个元件隔离区域包括在所述多个隧道绝缘膜之间沿着所述第一方向形成的多个沟槽，多个元件隔离膜填充在所述多个沟槽中，形成在所述多个元件隔离区域上并且沿着所述第二方向的所述多个电荷蓄积层的上表面和侧表面处于条形状的多个多晶硅绝缘膜，多个气隙形成在多个元件隔离膜之间填充在所述多个沟槽和所述多个多晶硅绝缘膜中，以及形成在所述多个多晶硅绝缘膜上的多个控制栅电极。

72. 发明授权

US07928496B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07928496B2
公开(公告)日：2011-04-19
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

73. 发明授权

US07919823B2 EEPROM array with well contacts 有权
标题翻译：具有良好触点的EEPROM阵列
公开(公告)号：US07919823B2
公开(公告)日：2011-04-05
申请号：US12716322
申请日：2010-03-03
申请人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
发明人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
IPC分类号： H01L29/24 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.
摘要翻译：一种半导体集成电路器件，包括：单元阱，形成在单元阱上的存储单元阵列，具有存储单元区域和单元阱接触区域，布置在存储单元区域中的第一布线体以及布置在单元阱中的第二布线体接触面积第二布线体的布局图案与第一布线体的布局图形相同。电池阱接触区域包括具有与电池阱相同的掺杂剂类型的电池阱触点，并且用作在电池阱接触区域中形成的虚拟晶体管的源极/漏极区域。

74. 发明授权

US07796439B2 Semiconductor memory device and write method thereof 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US07796439B2
公开(公告)日：2010-09-14
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C11/34 , G11C11/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

75. 发明授权

US07745884B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07745884B2
公开(公告)日：2010-06-29
申请号：US11870114
申请日：2007-10-10
申请人： Atsuhiro Sato , Fumitaka Arai , Yasuhiko Matsunaga
发明人： Atsuhiro Sato , Fumitaka Arai , Yasuhiko Matsunaga
IPC分类号： H01L27/105
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a source/drain diffusion layer, and a first select gate transistor which shares a source/drain diffusion layer with an endmost memory cell transistor that is located at one end of the series connection of the memory cell transistors and is adjacent to that memory cell transistor with a second gate spacing. The second gate spacing is set larger than the first gate spacing and the source/drain diffusion layer shared by the endmost memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by two adjacent memory cell transistors.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括以第一栅极间隔彼此串联连接的多个存储单元晶体管，存储单元晶体管的每两个相邻晶体管共享源极/漏极扩散层，以及共享源/漏扩散层的第一选择栅极晶体管，其具有位于存储单元晶体管的串联连接的一端并且具有第二栅极间隔的该存储单元晶体管的最末端的存储单元晶体管。第二栅极间隔被设定为大于第一栅极间隔，并且由最末端存储单元晶体管共享的源极/漏极扩散层，并且第一选择栅极晶体管包含杂质浓度高于源极/漏极扩散层所分配的源极/漏极扩散层的区域两个相邻的存储单元晶体管。

76. 发明授权

US07371654B2 Manufacturing method of semiconductor device with filling insulating film into trench 失效
标题翻译：具有填充绝缘膜的沟槽的半导体器件的制造方法
公开(公告)号：US07371654B2
公开(公告)日：2008-05-13
申请号：US11395134
申请日：2006-04-03
申请人： Atsuhiro Sato , Masayuki Ichige , Seiichi Mori , Yuji Takeuchi , Hiroaki Hazama , Yukio Nishiyama , Hirotaka Ogihara , Naruhiko Kaji
发明人： Atsuhiro Sato , Masayuki Ichige , Seiichi Mori , Yuji Takeuchi , Hiroaki Hazama , Yukio Nishiyama , Hirotaka Ogihara , Naruhiko Kaji
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
摘要翻译：根据HDP技术，在形成在半导体衬底的表面上或上方的沟槽的内表面上开始形成第一氧化硅膜。然后，第一氧化硅膜的沉积在沟槽的开口闭合之前停止。此外，蚀刻沉积在开口附近的第一氧化硅膜，并且根据HDP技术在沉积在沟槽底部的第一氧化硅膜上形成第二氧化硅膜。以这种方式，第一和第二氧化硅膜可以层压在沟槽的底部。

77. 发明申请

US20080061349A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH RESISTANCE ELEMENTS AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：具有电阻元件的非线性半导体存储器及其制造方法
公开(公告)号：US20080061349A1
公开(公告)日：2008-03-13
申请号：US11850978
申请日：2007-09-06
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

78. 发明申请

US20070287253A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070287253A1
公开(公告)日：2007-12-13
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

79. 发明申请

US20070159881A1 Nonvolatile semiconductor memory device including nand-type flash memory and the like 审中-公开
标题翻译：包括n型闪速存储器等的非易失性半导体存储器件
公开(公告)号：US20070159881A1
公开(公告)日：2007-07-12
申请号：US11474340
申请日：2006-06-26
申请人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro Sato , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

80. 发明申请

US20070109848A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20070109848A1
公开(公告)日：2007-05-17
申请号：US11553661
申请日：2006-10-27
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式