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71. 发明授权

US08102633B2 Power supply equalization circuit using distributed high-voltage and low-voltage shunt circuits 有权
标题翻译：电源均衡电路采用分布式高压和低压分流电路
公开(公告)号：US08102633B2
公开(公告)日：2012-01-24
申请号：US12406705
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路，耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

72. 发明授权

US08093957B1 Method and apparatus for frequency compensation for multi-band VCO 有权
标题翻译：用于多频带VCO频率补偿的方法和装置
公开(公告)号：US08093957B1
公开(公告)日：2012-01-10
申请号：US12561166
申请日：2009-09-16
申请人： Liang Zhang , Yong Wang , Xin Liu , Yu Zhang
发明人： Liang Zhang , Yong Wang , Xin Liu , Yu Zhang
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1265 , H03B5/1293
摘要： A method and apparatus for frequency compensation for multi-band VCO have been disclosed where a VCO tank loading capacitance is adjusted slowly to allow VCO operation in a linear range.
摘要翻译：已经公开了用于多频带VCO的频率补偿的方法和装置，其中VCO容器负载电容被缓慢调节以允许VCO在线性范围内操作。

73. 发明申请

US20120002573A1 DATA SIGNAL TRANSCEIVER CIRCUITRY FOR PROVIDING SIMULTANEOUS BI-DIRECTIONAL COMMUNICATION VIA A COMMON CONDUCTOR PAIR 有权
标题翻译：数据信号收发器电路，用于通过公共导体对提供同时的双向通信
公开(公告)号：US20120002573A1
公开(公告)日：2012-01-05
申请号：US13045301
申请日：2011-03-10
申请人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
发明人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
IPC分类号： H04L5/14
CPC分类号： H04L5/1415 , H04L5/1461 , H04L25/0276 , H04L25/0284 , H04L25/0296 , H04L25/0298 , H04L25/4904 , H04L67/12
摘要： Interface circuitry and method for transmitting and receiving downstream and upstream data signals simultaneously via a common conductor pair. The composite signal containing the downstream and upstream data signal components being conveyed by the common conductor pair is isolated, e.g., via signal filtering or buffering, and combined with an appropriately scaled inverse replica of the outgoing upstream data signal to subtract out upstream data signal components and thereby provide the downstream data signal substantially free of any upstream data signal components.
摘要翻译：用于经由公共导体对同时发送和接收下游和上游数据信号的接口电路和方法。包含由公共导体对传送的下游和上游数据信号分量的复合信号例如通过信号滤波或缓冲被隔离，并且与输出上行数据信号的适当缩放的反向副本相结合以减去上行数据信号分量从而提供基本上没有任何上行数据信号分量的下行数据信号。

74. 发明授权

US08073099B2 Differential interference phase contrast X-ray imaging system 有权
标题翻译：差分干涉相位对比X射线成像系统
公开(公告)号：US08073099B2
公开(公告)日：2011-12-06
申请号：US12426991
申请日：2009-04-21
申请人： Han-Ben Niu , Jin-Chuan Guo , Xin Liu
发明人： Han-Ben Niu , Jin-Chuan Guo , Xin Liu
IPC分类号： G01N23/083
CPC分类号： A61B6/00 , A61B6/4035 , A61B6/4233 , A61B6/4291 , A61B6/484 , G21K2207/005 , H01J35/08 , H01J2235/086
摘要： A differential phase-contrast X-ray imaging system is provided. Along the direction of X-ray propagation, the basic components are X-ray tube, filter, object platform, X-ray phase grating, and X-ray detector. The system provides: 1) X-ray beam from parallel-arranged source array with good coherence, high energy, and wider angles of divergence with 30-50 degree. 2) The novel X-ray detector adopted in present invention plays dual roles of conventional analyzer grating and conventional detector. The basic structure of the detector includes a set of parallel-arranged linear array X-ray scintillator screens, optical coupling system, an area array detector or parallel-arranged linear array X-ray photoconductive detector. In this case, relative parameters for scintillator screens or photoconductive detector correspond to phase grating and parallel-arranged line source array, which can provide the coherent X-rays with high energy.
摘要翻译：提供差分相位对比X射线成像系统。沿着X射线传播的方向，基本部件是X射线管，滤光片，物体平台，X射线相位光栅和X射线检测器。该系统提供：1）来自平行排列的源阵列的X射线束具有良好的相干性，高能量和更宽的发散角，具有30-50度的发散角度。 2）本发明所采用的新型X射线检测器具有传统分光光栅和传统探测器的双重作用。检测器的基本结构包括一组平行布置的线阵X射线闪烁体屏，光耦合系统，区域阵列检测器或平行排列的线阵X射线光电探测器。在这种情况下，闪烁体屏幕或光电导检测器的相对参数对应于相位光栅和平行布置的线源阵列，其可以提供具有高能量的相干X射线。

75. 发明申请

US20110206334A1 OPTICAL FIBRE SPLICING MODULE 审中-公开
标题翻译：光纤分离模块
公开(公告)号：US20110206334A1
公开(公告)日：2011-08-25
申请号：US12597995
申请日：2008-04-28
申请人： Xin Liu , Binqiang Zeng , Bin Liu , Xiaozhou Guo
发明人： Xin Liu , Binqiang Zeng , Bin Liu , Xiaozhou Guo
IPC分类号： G02B6/44
CPC分类号： G02B6/4454
摘要： The invention relates to an optical fibre splicing module. The optical fibre splicing module includes a base and a cover board, with two operation planes being arranged on the base, i.e. an upper operation plane provided with an optical fibre cable core winding area, a bare fibre winding and fusion welding area and an adapter holder, and a lower operation plane provided with a fibre pigtail winding area. 16 or 32 bayonets are arranged on the adapter holder, the bayonets are longitudinally arranged along the vertical direction of the operation planes. The size of the bayonets is just suitably connected to the vertically placed adapters. Not only the number of bayonets is increased to a number meeting the requirements of the optical splitter, but also the volume of the entire optical fibre splicing module can be ensured not to be increased by using the arrangement of the bayonets and the matching method of the bayonets with the vertically arranged adapters. Also, the integrity degree can be improved and the requirements of the optical splitter can be met, without changing the shape and size of existing adapters.
摘要翻译：本发明涉及一种光纤拼接模块。光纤拼接模块包括基座和盖板，底座上设有两个操作平面，即设置有光缆芯线圈区域的上操作平面，裸光纤绕组和熔焊区域以及适配器支架以及设置有纤维尾纤卷绕区域的下部操作面。 16或32个卡口布置在适配器支架上，卡口沿操作平面的垂直方向纵向布置。刺刀的尺寸只适合连接到垂直放置的适配器。不仅将卡口的数量增加到满足分光器要求的数量，还可以通过使用卡口的布置和匹配方法来确保整个光纤拼接模块的体积不增加卡口与垂直安装的适配器。此外，可以在不改变现有适配器的形状和尺寸的情况下，提高完整性程度并满足光分路器的要求。

76. 发明申请

US20110182286A1 SEPARATION DEVICE AND METHOD FOR TRANSMITTING VOICE SIGNAL 有权
标题翻译：分离设备和发送语音信号的方法
公开(公告)号：US20110182286A1
公开(公告)日：2011-07-28
申请号：US13078469
申请日：2011-04-01
申请人： Ke Zhang , Xin Liu
发明人： Ke Zhang , Xin Liu
IPC分类号： H04L12/66
CPC分类号： H04M1/738 , H04M1/2535 , H04M11/062 , H04M2203/2066
摘要： A separation device and a method for transmitting voice signal are disclosed. The separation device includes a line interface adapted to provide an interface for connecting to a telecommunication access system which provides public switched telephone network (PSTN) and data services; a data interface adapted to provide an interface connected with customer premises equipment (CPE) and connected with the line interface; a first communication interface adapted to provide an interface connected with a PSTN communication terminal; a second communication interface adapted to provide an interface connected with a foreign exchange station (FXS) interface of the CPE; and a connection switching unit adapted to connect the first communication interface with the line interface or connect the first communication interface with the second communication interface, and to perform switching between the two connections to implement PSTN communication or VoIP communication respectively. The solution in the embodiment may help perform switching with a PSTN communication terminal connection line according to different call types so that the PSTN communication terminal may implement the PSTN communication and the VoIP communication respectively.
摘要翻译：公开了一种用于发送语音信号的分离装置和方法。分离装置包括适于提供用于连接到提供公共交换电话网络（PSTN）和数据服务的电信接入系统的接口的线路接口; 数据接口，其适于提供与客户驻地设备（CPE）连接并且与线路接口连接的接口; 第一通信接口，适于提供与PSTN通信终端连接的接口; 第二通信接口，适于提供与所述CPE的外汇站（FXS）接口相连接的接口; 以及连接切换单元，其适于将所述第一通信接口与所述线路接口连接或者将所述第一通信接口与所述第二通信接口连接，并且在所述两个连接之间进行切换以分别实现PSTN通信或VoIP通信。本实施例的解决方案可以根据不同的呼叫类型来帮助用PSTN通信终端连接线进行切换，从而PSTN通信终端可以分别实现PSTN通信和VoIP通信。

77. 发明申请

US20110148838A1 BIAS CIRCUIT FOR A COMPLEMENTARY CURRENT MODE LOGIC DRIVE CIRCUIT 有权
标题翻译：用于补充电流模式逻辑驱动电路的偏置电路
公开(公告)号：US20110148838A1
公开(公告)日：2011-06-23
申请号：US12640180
申请日：2009-12-17
申请人： Kevin Yikai Liang , Xin Liu , Arvind Bomdica , Ming-Ju Edward Lee
发明人： Kevin Yikai Liang , Xin Liu , Arvind Bomdica , Ming-Ju Edward Lee
IPC分类号： G06F3/038 , G05F1/10
CPC分类号： H03K19/018514 , H03K19/018528
摘要： A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.
摘要翻译：电路包括互补电流模式逻辑驱动器电路和双反馈电流模式逻辑偏置电路。互补电流模式逻辑驱动器电路提供第一输出电压和第二输出电压。双反馈电流模式逻辑偏置电路包括第一反馈电路和第二反馈电路。第一反馈电路响应于第一输出电压为互补电流模式逻辑驱动器电路提供第一偏置电压。第二反馈电路响应于第二输出电压提供第二偏置电压。

78. 发明授权

US07590025B2 Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design 有权
标题翻译：在源同步DDR2接口设计中清洁DQS信号产生的系统和方法
公开(公告)号：US07590025B2
公开(公告)日：2009-09-15
申请号：US12004177
申请日：2007-12-19
申请人： Yong Wang , Liang Zhang , Xin Liu
发明人： Yong Wang , Liang Zhang , Xin Liu
IPC分类号： G11C8/18
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.
摘要翻译：提出了一种用于生成信号以同步存储器接口设计中的DQ数据传输的方法和电路。所提出的方法包括在数据传输脉冲串同步信号边沿转换之后接收具有在前后周期之前的前导码周期的选通信号，确定选通信号前导码周期的定时位置，确定选通信号后同步周期的定时位置并且产生干净的选通信号，其在选通信号前导码开始之后并且在选通信号后同步码结束之后，基于选通信号前导码和后置信号的相应确定的定时位置跟踪选通信号的数据传输脉冲串同步边沿转变，时间段以这种方式，DQ数据传输可以根据突发同步信号边沿转变和在前导码和后导码周期期间由选通信号电平抖动引起的错误来同步。

79. 发明授权

US07564454B1 Methods and displays having a self-calibrating delay line 有权
标题翻译：具有自校准延迟线的方法和显示器
公开(公告)号：US07564454B1
公开(公告)日：2009-07-21
申请号：US11005139
申请日：2004-12-06
申请人： Peter Shing , Xin Liu , Min Du , Qingping Zheng
发明人： Peter Shing , Xin Liu , Min Du , Qingping Zheng
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2085 , G09G2320/0693
摘要： A driver arrangement for a display includes at least one driver, such as a column driver, and a delay line arrangement coupled to the driver. The delay line arrangement delays a data signal provided to the driver by a delay period selectable from a plurality of possible delay periods. The delay line arrangement includes a calibration module that, when requested, is configured and arranged to adjust a current delay period produced by the delay line arrangement towards a predetermined delay period. Displays can include the driver arrangement to provide self-calibration of the delay line.
摘要翻译：用于显示器的驱动器装置包括至少一个驱动器，例如列驱动器，以及耦合到驱动器的延迟线布置。延迟线布置将提供给驱动器的数据信号延迟可从多个可能的延迟周期中选择的延迟周期。延迟线布置包括校准模块，其在被请求时被配置和布置成将延迟线布置产生的电流延迟周期调整到预定的延迟周期。显示器可以包括驱动器装置以提供延迟线的自校准。

80. 发明申请

US20090161452A1 Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design 有权
公开(公告)号：US20090161452A1
公开(公告)日：2009-06-25
申请号：US12004177
申请日：2007-12-19
申请人： Yong Wang , Liang Zhang , Xin Liu
发明人： Yong Wang , Liang Zhang , Xin Liu
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.

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