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71. 发明申请

US20080123792A1 Apparatus and method for transmitting signals over a signal line 审中-公开
标题翻译：通过信号线传输信号的装置和方法
公开(公告)号：US20080123792A1
公开(公告)日：2008-05-29
申请号：US11604649
申请日：2006-11-27
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： H04L7/04
CPC分类号： H04L7/06 , H04L7/08 , H04L25/0272 , H04L25/0286 , H04L25/45
摘要： An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.
摘要翻译：用于通过信号线传输信号的装置包括具有可连接到信号线的输出的发射机，用于在功率节省模式下的同步信号和在正常操作模式下的有用信号，其中同步信号具有减小的幅度与所需信号的幅度相比较，并且具有周期性数据模式，使得同步信号允许在接收机中保持同步信号和参考信号的对准。

72. 发明授权

US07362622B2 System for determining a reference level and evaluating a signal on the basis of the reference level 有权
标题翻译：用于确定参考电平并基于参考电平评估信号的系统
公开(公告)号：US07362622B2
公开(公告)日：2008-04-22
申请号：US11099222
申请日：2005-04-05
申请人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
发明人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
IPC分类号： G11C7/10 , G11C7/20 , G06F9/00
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译：电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。此外，电路还具有用于基于参考电平来评估信号的装置。

73. 发明授权

US07342815B2 DQS signaling in DDR-III memory systems without preamble 有权
标题翻译：没有前导码的DDR-III存储器系统中的DQS信号
公开(公告)号：US07342815B2
公开(公告)日：2008-03-11
申请号：US11214067
申请日：2005-08-30
申请人： Hermann Ruckerbauer , Georg Braun , Amir Motamedi
发明人： Hermann Ruckerbauer , Georg Braun , Amir Motamedi
IPC分类号： G11C5/06
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.
摘要翻译：特别是作为DDR-III存储器芯片通信电路的一部分的数据传输系统执行无前导码的数据传输操作。该数据传输系统包括至少一条具有可接通和关断的管芯端接的数据线，并且数据线的芯片端连接到正极或接地或负极的电源电压线通过上拉或下拉电阻。或者，数据传输系统的操作是在相应的运行状态下接通的终端电路不被打开的定时，直到被激活的驱动程序被激活为止。

74. 发明授权

US07275189B2 Memory module and method for operating a memory module in a data memory system 有权
标题翻译：用于操作数据存储器系统中的存储器模块的存储器模块和方法
公开(公告)号：US07275189B2
公开(公告)日：2007-09-25
申请号：US10724135
申请日：2003-12-01
申请人： Hermann Ruckerbauer , Georg Braun
发明人： Hermann Ruckerbauer , Georg Braun
IPC分类号： G11C29/00
CPC分类号： G11C7/1066 , G11C7/1006
摘要： Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality for conditioning data signals that are transferred to the memory module and output from the memory module and is suitable for the correction of user data stored erroneously in the DDR-DRAMs. The buffer and error checking module enables the integration of both error correction and buffer/redriver functionality on memory modules within the restricted memory module dimensions in accordance with definitive industry standards, simplified or improved routing of data lines and of control and address lines and also, by virtue of a reduction of erroneously transferred data to the data memory system, an increased real data transfer rate.
摘要翻译：基于DDR-DRAM的内存模块提供了一个缓冲区和错误检查模块，该模块集成了错误数据存储器和缓冲/转移功能，用于调节传输到存储器模块并从存储器模块输出的数据信号，适用于在DDR-DRAM中错误地存储的用户数据的校正。缓冲区和错误检查模块使得能够根据确定的行业标准，数据线以及控制和地址线的简化或改进路由，在受限存储器模块尺寸内的存储器模块上集成纠错和缓冲/转移功能，通过减少错误传送的数据到数据存储系统，增加了实际的数据传输速率。

75. 发明授权

US07272063B1 Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory 有权
标题翻译：具有温度传感器，动态存储器和具有时钟单元的存储器的存储器以及感测存储器温度的方法
公开(公告)号：US07272063B1
公开(公告)日：2007-09-18
申请号：US11386048
申请日：2006-03-21
申请人： Jens Christoph Egerer , Georg Braun
发明人： Jens Christoph Egerer , Georg Braun
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/16 , G11C11/406 , G11C11/40626 , G11C2211/4061 , G11C2211/4067
摘要： Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.
摘要翻译：用于确定存储器件的温度的方法和装置。存储器件包括存储器阵列，被配置为测量器件的温度的温度以及被配置为接收表示由温度传感器测量的温度的信号并被配置为产生指示测量温度的代码字的评估电路，以及温度传感器的类型，温度传感器从至少两种不同的温度传感器类型中的一种中选择。

76. 发明申请

US20060227627A1 Buffer component for a memory module, and a memory module and a memory system having such buffer component 有权
标题翻译：用于存储器模块的缓冲器组件，以及具有这种缓冲器组件的存储器模块和存储器系统
公开(公告)号：US20060227627A1
公开(公告)日：2006-10-12
申请号：US11368267
申请日：2006-03-03
申请人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
发明人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
IPC分类号： G11C7/10
CPC分类号： G11C5/063 , G06F13/1689 , G11C5/04 , G11C7/1078 , G11C7/109
摘要： The invention relates to a buffer component for a memory module having a plurality of memory components, comprising a first data interface for receiving an item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.
摘要翻译：本发明涉及一种用于具有多个存储器组件的存储器模块的缓冲器组件，包括：第一数据接口，用于根据数据传输协议接收访问信息项，地址，时钟，控制和命令信号取决于访问信息，用于驱动时钟信号的第二数据接口，以及对多个存储器组件的地址和命令信号，以及根据信令协议将控制信号驱动到多组存储器组件的一组，其中激活存储器组件和地址和命令信号的接受以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件并应用所述控制信号用于将所述多个存储器组件的组激活到所述多个组中的组在时钟信号的随后的第二时钟周期中存在地址和命令信号时被激活的多路分量，由此存在的地址和命令信号被接收到多个存储器组件的组中。

77. 发明申请

US20060202328A1 Memory module and memory configuration with stub-free signal lines and distributed capacitive loads 审中-公开
标题翻译：内存模块和内存配置，无短信号线和分布式容性负载
公开(公告)号：US20060202328A1
公开(公告)日：2006-09-14
申请号：US11431765
申请日：2006-05-10
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： H01L23/34
CPC分类号： G11C5/063 , G11C5/04 , H01L2224/16225 , H05K1/14
摘要： In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.
摘要翻译：在具有由多个信号线构成的总线系统的存储器配置的存储器模块中，每个信号线分别基本上没有从供电接触装置连续地到达放电接触装置的任何短截线，放电接触装置靠近供电接点设备，以便在内存配置中增加最大数据传输速率。在供电接触装置和放电接触装置之间，通过与与信号线相关联的存储器芯片上的信号线相关联的连接元件，以最小距离连续路由每条信号线。

78. 发明授权

US06958613B2 Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit 失效
标题翻译：使用公共校准基准和校准电路校准半导体器件的方法
公开(公告)号：US06958613B2
公开(公告)日：2005-10-25
申请号：US10675492
申请日：2003-09-30
申请人： Georg Braun , Hermann Ruckerbauer , Simon Muff
发明人： Georg Braun , Hermann Ruckerbauer , Simon Muff
IPC分类号： G01R35/00 , G06F11/24 , G06F11/27 , G06F13/38 , G11C7/10 , G11C29/02 , H04L7/04
CPC分类号： G11C29/022 , G06F11/24 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die termination) for double data rate dynamic random access memories, are aligned using a calibration reference which is common to the semiconductor devices and is connected to calibration connections on the semiconductor devices. The semiconductor devices are calibrated in succession, in each case individually, and the calibration connection on the respective semiconductor device which is currently performing calibration is connected to an internal calibration unit by an internal switching unit in the process, and the calibration connections on all other semiconductor devices are terminated to a high impedance internally.
摘要翻译：用于双数据速率动态随机存取存储器的多个半导体器件的接口参数，特别是用于输出驱动器（即片上驱动器）的参数和终端（即，芯片端接）的参数使用半导体器件公共的校准参考并连接到半导体器件上的校准连接。半导体器件在每种情况下分别校准，并且当前正在执行校准的相应半导体器件上的校准连接通过该过程中的内部切换单元连接到内部校准单元，并且所有其他校准连接半导体器件在内部被端接到高阻抗。

79. 发明授权

US06724685B2 Configuration for data transmission in a semiconductor memory system, and relevant data transmission method 有权
标题翻译：半导体存储器系统中数据传输的配置及相关数据传输方法
公开(公告)号：US06724685B2
公开(公告)日：2004-04-20
申请号：US10284773
申请日：2002-10-31
申请人： Georg Braun , Hermann Ruckerbauer
发明人： Georg Braun , Hermann Ruckerbauer
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/10 , G11C7/1051 , G11C2207/2254
摘要： In a configuration for data transmission in a semiconductor memory system, in which data are transmitted between at least one semiconductor memory module and a memory controller controlled by a system clock signal, additional sense clock signal lines are led between the memory controller and the memory modules and, via loops on the memory modules, are led back directly from the memory modules to the memory controller component. By transmitting a sense clock signal from the memory controller to each of the memory modules via the additional sense clock signal lines, the memory controller is able to measure the respective signal propagation time of the sense clock signal and adjust a delay time for the data signals respectively received from the memory modules appropriately. The use of a data strobe signal and the associated disadvantages when testing the memory system or the memory modules is rendered superfluous.
摘要翻译：在半导体存储器系统中的数据传输配置中，在至少一个半导体存储器模块和由系统时钟信号控制的存储器控制器之间传输数据，在存储器控制器和存储器模块之间引导附加感测时钟信号线并且通过存储器模块上的循环被直接从存储器模块引导回存储器控制器组件。通过经由附加感测时钟信号线将存储器控制器的感测时钟信号从存储器控制器发送到每个存储器模块，存储器控制器能够测量感测时钟信号的相应信号传播时间并且调整数据信号的延迟时间分别从内存模块分别接收。当测试存储器系统或存储器模块时，使用数据选通信号和相关的缺点是多余的。

80. 发明授权

US06715138B2 Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement 失效
标题翻译：用于组合基于逻辑的电路单元和基于存储器的电路单元和电路布置的方法
公开(公告)号：US06715138B2
公开(公告)日：2004-03-30
申请号：US10164453
申请日：2002-06-06
申请人： Georg Braun
发明人： Georg Braun
IPC分类号： G06F1750
CPC分类号： G06F1/26
摘要： A method for combining logic-based circuit units and memory-based circuit units in a common circuit arrangement is provided. The different supply voltage swings are fed to the different units wherein a signal voltage swing at a connection line between the memory-based circuit unit and the logic-based circuit unit is adjusted such that in the case of logic-based circuit units the signal voltage swing is provided in the range between a signal voltage minimum value of 0.4V and a signal voltage maximum value of 0.8V.
摘要翻译：提供了一种用于在公共电路装置中组合基于逻辑的电路单元和基于存储器的电路单元的方法。不同的电源电压摆动被馈送到不同的单元，其中调整基于存储器的电路单元和基于逻辑的电路单元之间的连接线处的信号电压摆动，使得在基于逻辑的电路单元的情况下，信号电压在0.4V的信号电压最小值和0.8V的信号电压最大值之间的范围内提供摆幅。

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