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71. 发明授权

US06188113B1 High voltage transistor with high gated diode breakdown, low body effect and low leakage 有权
标题翻译：具有高门极二极管击穿的高压晶体管，低体积效应和低漏电流
公开(公告)号：US06188113B1
公开(公告)日：2001-02-13
申请号：US09502347
申请日：2000-02-10
申请人： Narbeh Derhocobian , Pau-ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhocobian , Pau-ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L31119
CPC分类号： H01L29/66575 , H01L21/76216 , H01L29/0692 , H01L29/66659 , H01L29/78
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
摘要翻译：形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

72. 发明授权

US5708588A Flash EEPROM memory with improved discharged speed using substrate bias and method therefor 失效
标题翻译：闪存EEPROM存储器，使用衬底偏置改善放电速度及其方法
公开(公告)号：US5708588A
公开(公告)日：1998-01-13
申请号：US464024
申请日：1995-06-05
申请人： Sameer S. Haddad , Hao Fang
发明人： Sameer S. Haddad , Hao Fang
IPC分类号： G11C16/14 , H01L29/788 , G06F15/00 , G11C11/40
CPC分类号： H01L29/7885 , G11C16/14 , Y10S438/972
摘要： A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.
摘要翻译：具有改善的放电速度的浮动栅极单元存储器件，例如EPROM或快闪EEPROM。在放电期间，对有效衬底施加负偏压。负偏压增加了接点附近的电场，从而增加了可以注入到浮动栅极的热孔数量，从而提高了放电速度。

73. 发明授权

US5606518A Test method for predicting hot-carrier induced leakage over time in short-channel IGFETS and products designed in accordance with test results 失效
标题翻译：用于预测短路IGFETS中热载流子诱导的漏电的测试方法以及根据测试结果设计的产品
公开(公告)号：US5606518A
公开(公告)日：1997-02-25
申请号：US442320
申请日：1995-05-16
申请人： Hao Fang , Peng Fang , John T. Yue
发明人： Hao Fang , Peng Fang , John T. Yue
IPC分类号： G01R31/26 , G01R31/30 , G01R31/317 , G06F11/26 , G06F17/50 , G01R19/145 , G01R31/28
CPC分类号： G01R31/2621 , G01R31/3004 , G01R31/31707 , G06F17/5036 , G06F11/261
摘要： A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.
摘要翻译：提供了一种测试方法和装置，用于在IGFET中预测随时间推移的热载流子诱发的泄漏。测试结果用于显示通道长度和应力电压的选择如何随着时间的推移严重影响热载体引起的泄漏（HCIL）泄漏，特别是在具有亚微米通道长度的器件中。由于短期测试结果，模型用于长期预测泄漏电流。提出了可靠地满足长期泄漏要求的替代设计策略。

74. 发明授权

US08329530B1 Method and system for providing contact to a first polysilicon layer in a flash memory device 有权
标题翻译：用于提供与闪存器件中的第一多晶硅层的接触的方法和系统
公开(公告)号：US08329530B1
公开(公告)日：2012-12-11
申请号：US13566741
申请日：2012-08-03
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/11521 , H01L21/76816 , H01L27/115
摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤不会蚀刻通过多晶硅层。该方法和系统还包括用导体填充至少一个接触孔。

75. 发明申请

US20120121692A1 COMPOUNDS AND COMPOSITIONS COMPRISING CDK INHIBITORS AND METHODS FOR TREATING CANCER 审中-公开
标题翻译：包含CDK抑制剂的化合物和组合物以及治疗癌症的方法
公开(公告)号：US20120121692A1
公开(公告)日：2012-05-17
申请号：US13318519
申请日：2010-05-07
申请人： Wen Fang Xu , Hao Fang , Yan Ling Li , Binghe Wang
发明人： Wen Fang Xu , Hao Fang , Yan Ling Li , Binghe Wang
IPC分类号： A61K9/127
CPC分类号： C07D213/50 , A61K31/35 , A61K45/06 , C07D295/112 , C07D307/46 , C07D405/04 , A61K2300/00
摘要： Disclosed herein are compounds suitable for use as antitumor agents, methods for treating cancer wherein the disclosed compounds are used in making a medicament for the treatment of cancer, methods for treating a tumor comprising, administering to a subject a composition comprising one or more of the disclosed cytotoxic agents, and methods for preparing the disclosed antitumor agents.
摘要翻译：本文公开了适合用作抗肿瘤剂的化合物，用于治疗癌症的方法，其中所公开的化合物用于制备用于治疗癌症的药物，用于治疗肿瘤的方法，包括向受试者施用包含一种或多种公开的细胞毒剂，以及制备所公开的抗肿瘤剂的方法。

76. 发明授权

US07692887B2 Method and apparatus for measuring resistance of a resistive sensor 有权
标题翻译：用于测量电阻式传感器电阻的方法和装置
公开(公告)号：US07692887B2
公开(公告)日：2010-04-06
申请号：US11520493
申请日：2006-09-13
申请人： Daniel J. Dolan, Jr. , Hao Fang , Jeffrey A. Gleason , Ross S. Wilson
发明人： Daniel J. Dolan, Jr. , Hao Fang , Jeffrey A. Gleason , Ross S. Wilson
IPC分类号： G11B27/36
CPC分类号： G11B5/455 , G11B2005/0016
摘要： An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.
摘要翻译：一种用于确定电阻头的头部参数值（例如，头部电阻）的装置和方法。在头部参数测量间隔期间，使用在操作（读取操作）间隔期间向头部提供偏置电流的相同电流源向头部提供测试头电流。确定的头参数值被锁存用于设置在操作间隔期间控制电流源的控制回路的控制回路增益。

77. 发明申请

US20080062551A1 Method and apparatus for measuring resistance of a resistive sensor 有权
标题翻译：用于测量电阻式传感器电阻的方法和装置
公开(公告)号：US20080062551A1
公开(公告)日：2008-03-13
申请号：US11520493
申请日：2006-09-13
申请人： Daniel J. Dolan , Hao Fang , Jeffrey A. Gleason , Ross S. Wilson
发明人： Daniel J. Dolan , Hao Fang , Jeffrey A. Gleason , Ross S. Wilson
IPC分类号： G11B27/36 , G11B5/03
CPC分类号： G11B5/455 , G11B2005/0016
摘要： An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.
摘要翻译：一种用于确定电阻头的头部参数值（例如，头部电阻）的装置和方法。在头部参数测量间隔期间，使用在操作（读取操作）间隔期间向头部提供偏置电流的相同电流源向头部提供测试头电流。确定的头参数值被锁存用于设置在操作间隔期间控制电流源的控制回路的控制回路增益。

78. 发明申请

US20070147118A1 METHODS FOR ACTIVE BOOSTING TO MINIMIZE CAPACITIVE COUPLING EFFECT BETWEEN ADJACENT GATES OF FLASH MEMORY DEVICES 有权
标题翻译：用于主动加速以最小化闪存存储器件相邻栅极之间的电容耦合效应的方法
公开(公告)号：US20070147118A1
公开(公告)日：2007-06-28
申请号：US11319260
申请日：2005-12-27
申请人： Tuan Pham , Masaaki Higashitani , Hao Fang , Gerrit Hemink
发明人： Tuan Pham , Masaaki Higashitani , Hao Fang , Gerrit Hemink
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

79. 发明授权

US07221008B2 Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory 有权
标题翻译：位线方向屏蔽，以避免NAND闪存相邻单元之间的交叉耦合
公开(公告)号：US07221008B2
公开(公告)日：2007-05-22
申请号：US10680665
申请日：2003-10-06
申请人： George Matamis , Tuan Pham , Henry Chien , Hao Fang
发明人： George Matamis , Tuan Pham , Henry Chien , Hao Fang
IPC分类号： H01L29/80 , H01L31/112 , H01L21/336 , G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/115
摘要： A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from disturbs.
摘要翻译：一种NAND闪速存储器结构和方法，其制造具有在位线方向上的屏蔽的闪存结构以及来自Yupin的字线和对角线方向的效果误差和干扰。

80. 发明申请

US20060227446A1 Over-writing data in a recording system 有权
标题翻译：在录音系统中重写数据
公开(公告)号：US20060227446A1
公开(公告)日：2006-10-12
申请号：US11100162
申请日：2005-04-06
申请人： Carl Elliott , Hao Fang , Ross Wilson
发明人： Carl Elliott , Hao Fang , Ross Wilson
IPC分类号： G11B20/10 , G11B21/02
CPC分类号： G11B20/1403 , G11B5/012 , G11B20/00086 , G11B20/0021 , G11B20/00579 , G11B20/10009 , G11B20/10425 , G11B2020/10898 , G11B2220/2516
摘要： A recording system stores recording cycle information identifying the parameters for recording user data on a particular data sector. During a subsequent operation, the recording system employs the recording cycle information to select a different set of parameters for recording new user data at the particular data sector. One of the parameters might identify a recorded pattern in a balance pad at the data sector, and another one of the parameters might identify a scrambler seed value. By employing a different set of recording parameters for each occurrence of recording user data at the particular sector, sample timing of, for example, a read channel might be based on an average of easy and hard transitions.
摘要翻译：记录系统存储识别用于在特定数据扇区上记录用户数据的参数的记录周期信息。在随后的操作期间，记录系统采用记录周期信息来选择用于在特定数据扇区记录新用户数据的不同参数集合。参数中的一个可以识别数据扇区中的平衡衬垫中的记录模式，另一个参数可以识别加扰器种子值。通过对特定扇区的记录用户数据的每次出现采用不同的记录参数集合，例如读通道的采样定时可以基于简单和硬转换的平均值。

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