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71. 发明专利

JPH04324587A METHOD AND DEVICE FOR RECOGNIZING PATTERN/DISPLAYING FAIR COPY, GRAPHIC INPUT DEVICE, AND DRAWING DEVICE 失效
公开(公告)号：JPH04324587A
公开(公告)日：1992-11-13
申请号：JP9516391
申请日：1991-04-25
申请人： HITACHI LTD
发明人： YOKOTA TOSHIMI , SHOJIMA HIROSHI , MIURA MASAKI , KUZUNUKI SOUSHIROU , FUKUNAGA YASUSHI , OTSUKA YUSAKU
IPC分类号： G06F3/041 , G06F3/03 , G06F3/048 , G06F3/14 , G06T3/00 , G06T7/00 , G06T7/60
摘要： PURPOSE:To display a tentative pattern recognized result against input pattern data at prescribed timing at any time even the input of the recognizing unit of the input pattern data is not completed. CONSTITUTION:While the display of a handwritten input pattern is displayed on a display 10, a recognizing section 3 tentatively recognizes the input pattern while the pattern is inputted at recognition actuating timing which is generated at any time irrespective of the pattern input to a pattern input section 1 by recognizing units and the tentatively recognized pattern is displayed in a fair copy instead of the handwritten input pattern until the section 3 obtains the pattern recognized result of the final recognizing unit of the input pattern.

72. 发明专利

JPH02232784A CLIPPING METHOD AND GRAPHIC SYSTEM AND WORK STATION 失效
公开(公告)号：JPH02232784A
公开(公告)日：1990-09-14
申请号：JP5277589
申请日：1989-03-07
申请人： HITACHI LTD
发明人： FUKUNAGA YASUSHI , FUJITA MAKOTO , KOGA KAZUYOSHI , HARA HIDEYUKI
IPC分类号： G06T11/00
摘要： PURPOSE:To execute the display processing of a graphic, etc., at a high speed by taking a clipping deciding area wider than an actual picture drawing area, and displaying only data which goes into the picture drawing area among image data which are decided to be brought to picture drawing. CONSTITUTION:In the case of displaying a straight line in a picture drawing area of a window opened in a screen, a main processor 10 writes a command of its fact and coordinates of both end points of the straight line into a shared memory 11, and commands the starting to a processor 12 through a bus 14. The processor 12 reads out the command and a coordinate of a picture drawing area and the coordinates of both the end points from the memory 11 and converts them into coordinates of a device coordinate system, and also, sets a clipping (CL) area to the picture drawing area, and decides whether the straight line goes into its area or not. In the case when only a part of the straight line goes into its area, a coordinate of an intersection of the straight line and a borderline of the CL area is derived, its coordinate and the coordinate of the end point of the straight line in the CL area are delivered to a processor 13, a picture element for connecting both the coordinate points is developed and written in a frame memory 16, and also, the straight line is displayed 17 in the picture drawing area of the window.

73. 发明专利

JPH01177685A RENDERING PROCESSOR AND SCREEN DISPLAY DEVICE 失效
公开(公告)号：JPH01177685A
公开(公告)日：1989-07-13
申请号：JP120388
申请日：1988-01-08
申请人： HITACHI LTD
发明人： FUJITA MAKOTO , FUKUNAGA YASUSHI , KOGA KAZUYOSHI , YASUDA ISAO , KATO TAKESHI
IPC分类号： G06F3/153 , G06F15/16 , G06F15/80 , G06T11/20
摘要： PURPOSE:To shorten the response time of a screen display by providing plural processor elements to parallel-process a signal from a display control processor and a synchronizing means to synchronize a processing between plural processor elements. CONSTITUTION:A rendering processor to execute the processing to frame memories 5-1-5-11 is divided into plural processor elements 4-1-4-11, and the synchronizing means to synchronize the processing between plural processor elements 4-1-4-11 is provided. Namely, the rendering processor is composed of plural processor elements 4-1-4-11, one processor element 4 is specified as a master processor element by an identifying signal 41, a synchronizing signal 42 is outputted, other plural processor elements which are slave processor elements input the synchronizing signal 42, and all processor elements start the processing in synchronizing. Thus, the parallel processing can be executed, and a high-speed processing can be executed.

74. 发明专利

JPH01124895A ACCESS APPARATUS FOR IMAGE MEMORY 失效
公开(公告)号：JPH01124895A
公开(公告)日：1989-05-17
申请号：JP24111688
申请日：1988-09-28
申请人： HITACHI LTD
发明人： FUJITA MAKOTO , FUKUNAGA YASUSHI
IPC分类号： G09G5/00 , G06F12/00 , G06T1/60 , G06T11/00 , G09G1/00 , G09G1/02 , G09G5/02 , G09G5/32 , G09G5/36 , G09G5/38
摘要： PURPOSE: To shorten the processing time required to copy picture data to another place by providing an arithmetic unit in each layer of a picture memory and merging picture data held in two registers in each arithmetic unit and performing shift and logical operation. CONSTITUTION: Arithmetic units 111 to 11N are connected to picture memories 101 to 10N through local busses 121 to 12N. A controller 5 sends a source address to a bus 3 and holds data of the corresponding picture memory in a register 202 in the arithmetic unit and sends the address obtained by adding one to the source address. Contents of the register 202 are moved to a register 203, and data in this address is held in the register 202. Next, the controller 5 gives a transfer destination address and takes picture data into a register 208. Desired data in data of registers 202 and 203 is subjected to logical operation together with data in the register 208 by a computing element 205, and the result is written in the transfer destination address through a mask selector 206 and a register 207. Thus, the processing time for copy to another place is shortened.

75. 发明专利

JPS6448174A FRAME MEMORY ADDRESS CONVERTING CIRCUIT 失效
公开(公告)号：JPS6448174A
公开(公告)日：1989-02-22
申请号：JP20414387
申请日：1987-08-19
申请人： HITACHI LTD
发明人： KOGA KAZUYOSHI , FUKUNAGA YASUSHI , FUJITA MAKOTO , NISHIDA TAKEHIKO
IPC分类号： G06F12/00 , G06F3/153 , G06F13/16 , G06T1/60
摘要： PURPOSE:To constitute a frame memory, which has the double buffer constitution, of a small number of memory chips by performing such frame memory address conversion that one memory chip supports the access to the front buffer and that to the rear buffer. CONSTITUTION:A frame buffer controller 3 is provided with a register which indicates whether the access to a frame memory 4 is the access to the front buffer of the frame memory 4 or the access to the rear buffer, a linear address converting circuit which assigns the Y address to the side of upper bits of the X address, an inverting address converting circuit which inverts plural bits of address bits, and a selector which selects the output of one of two address converting circuits in accordance with the instruction of the register and uses this selected output as the access address of the frame memory 4. Thus, the number of memory chips constituting the frame memory is reduced in case of the double buffer constitution, and address conversion for the frame memory is quickly performed.

76. 发明专利

JPS63266513A BUS CONTROL SYSTEM 失效
公开(公告)号：JPS63266513A
公开(公告)日：1988-11-02
申请号：JP9984587
申请日：1987-04-24
申请人： HITACHI LTD
发明人： YUNO KAZUHARU , NISHIDA TAKEHIKO , FUKUNAGA YASUSHI
IPC分类号： G06F13/40 , G06F3/00
摘要： PURPOSE:To prevent a simultaneous ON state (output state) of a bus signal line to which a three state gate having a totem pole structure has been brought to wired OR connection, by giving two pieces of common signal machines (clock signals) to an enable/disable switching control part. CONSTITUTION:With respect to an enable timing of an output gate 3 of a signal line which has the possibility that it becomes a simultaneous ON state (output state) and has been brought to wired OR connection, an enable condition is prescribed by a signal line which has no possibility that it becomes the simultaneous ON state (output state), and said timing becomes a fall or rise timing of an enable timing prescribing clock signal 1 at the time point when said condition has been satisfied. Also, a disable timing of this output gate 3 is set as a fall or rise timing time of a disable timing time of a disable timing prescribing clock signal 2. In such a way, the simultaneous ON state (output state) does not occur.

77. 发明专利

JPS63247878A DRAWING ADDRESS ARITHMETIC UNIT 失效
公开(公告)号：JPS63247878A
公开(公告)日：1988-10-14
申请号：JP8121187
申请日：1987-04-03
申请人： HITACHI LTD
发明人： KOGA KAZUYOSHI , FUKUNAGA YASUSHI , FUJITA MAKOTO , NISHIDA TAKEHIKO
IPC分类号： G06T1/00 , G06T11/20
摘要： PURPOSE:To perform quick drawing by calculating parameters required for drawing address generation of an area in device's charge based on initial parameters in accordance with an integer type incremental algorithm. CONSTITUTION:Digital differential analyzers (DDA) 31 and 32 simultaneously calculate an address in accordance with the incremental algorithm, and the address in the direction of a line to be drawn is outputted by the pair of DDAs 31 and 32. Effective bits and upper bits from DDAs are sent to a write control circuit 33, and effective bits and lower bits are sent to corresponding data generating circuits 41 and 42. A synthesizing circuit 43 masks bits in pixel positions other than bits corresponding to display pixels by data from data generating circuits 41 and 42. Obtained picture data is written in a frame memory by the indication of the write control circuit 33.

78. 发明专利

JPS63131275A INTERPICTURE ARITHMETIC UNIT 失效
公开(公告)号：JPS63131275A
公开(公告)日：1988-06-03
申请号：JP27656686
申请日：1986-11-21
申请人： HITACHI LTD
发明人： KAWABATA ATSUSHI , FUKUNAGA YASUSHI , WATANABE NORITO , TANIFUJI SHINYA
IPC分类号： G06F3/153 , G06T3/00
摘要： PURPOSE:To find an exclusive 'OR' between binary pictures by calculating the absolute value of a difference at every point in two pieces of pictures and outputting the value as output picture. CONSTITUTION:Input pictures 1 and 2 are given to an interpicture arithmetic unit 3. It compares density information expressed in numerics at every point between two pictures 1 and 2 holding density information, and sets the absolute value of the difference to a density value on the point corresponding to an output picture 4. The interpicture arithmetic unit 3 consists of a maximum value detection circuit, a minimum value detection circuit and a difference arithmetic circuit, for example.

79. 发明专利

JPS6321944B2 失效
公开(公告)号：JPS6321944B2
公开(公告)日：1988-05-10
申请号：JP5241681
申请日：1981-04-09
申请人： HITACHI LTD
发明人： YANAI HIDEO , NAKANISHI HIROAKI , KOBAYASHI HIROSHI , FUKUNAGA YASUSHI
IPC分类号： G06F13/00 , G06F9/52 , G06F11/30 , G06F13/42 , G06F15/16 , G06F15/177

80. 发明专利

JPS6337465A KANA/KANJI CONVERTER 失效
公开(公告)号：JPS6337465A
公开(公告)日：1988-02-18
申请号：JP17998186
申请日：1986-08-01
申请人： HITACHI LTD
发明人： FUKUNAGA YASUSHI , KUZUNUKI SOSHIRO , SHOJIMA HIROSHI
IPC分类号： G06F17/22
摘要： PURPOSE:To contrive the improve efficiency that converts a pair of KANJI (Chinese character) including KANA (Japanese syllabary) by temporarily converting a KANJI part included in an input character string into KANA, comparing an output obtained by converting KANA into KANJI with the KANJI part included in the input character string and outputting the same KANJI. CONSTITUTION:When a character is inputted with a pen from a handwritten input device 1, it recognizes the inputted character, converts it into a character code 11, and transmits said code to a KANJI converter 2. A KANJI extraction part separates a KANJI code, a KANA code and other codes from the character code string. The KANJI code is transmitted both to a KANJI dictionary and to a comparator 4. The KANJI dictionary stores the reading of the corresponding KANJI code as data. The comparator 4 compares the KANJI code that a KANJI conversion part 3 converts with the KANJI code 15 of KANJI included in the inputted character that the KANJI converter 2 extracts, and checks whether they are the same In such a way KANA/KANJI conversion is attainable in consideration of information on the KANJI code in the input code string.

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