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71. 发明专利

JPS6389669A COOLING TYPE VAPOR PHASE REACTION APPARATUS 失效
公开(公告)号：JPS6389669A
公开(公告)日：1988-04-20
申请号：JP23600686
申请日：1986-10-03
申请人： HITACHI ELECTR ENG
发明人： OYAMA KATSUMI , HIKIMA HITOSHI , TANIGUCHI KAZUO , YOSHIDA AKIRA , MURAKAWA YUKIO , TAKAMI KATSUMI , KISHIMOTO SATORU
IPC分类号： H01L21/31 , C23C16/40 , C23C16/44
摘要： PURPOSE:To prevent the deposition of foreign matter fine particle flakes on the inside wall surface of a reaction furnace by providing cooling means each having a reduced pressure space to the outside wall surface of the reaction furnace, supplying water into said means and maintaining a reduced pressure state in said spaces to evaporate the water, thereby cooling the wall surface. CONSTITUTION:Plural pieces of the cooling means 20 each having the reduced pressure space 18 are provided to the outside wall surface of the reaction furnace nearly over the entire surface thereof. Each means 20 is provided with a water supply pipe 22, a vacuum suction port 24 and a drain port 26. While the flow rate of the water is controlled by a valve 28, the water is supplied from a port end 34 of the pipe 22 so that the water flows uniformly along the wall surface 32 on the outside wall surface side of the reaction furnace. The air in the spaces 18 of the means 20 is evacuated to generate the reduced pressure state by a pump 36 from the ports 24 by which the water is flash-evaporated and the surface 32 is cooled. The excess water which is not evaporated is passed from the ports 26 into a drain tank 40. A valve 42 is closed when the water accumulates into the tank. The accumulated water is removed by opening an atm. intake valve 44 and a drain valve 46. The entire wall surface of the reaction furnace is thereby efficiently and uniformly cooled and the formation and deposition of the flakes of the foreign matter fine particles thereon are prevented.

72. 发明专利

JP2002368078A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2002368078A
公开(公告)日：2002-12-20
申请号：JP2001171903
申请日：2001-06-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSHINO MASAKAZU , SEKI HIROBUMI , OYAMA KATSUMI , NUMATA YUKI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/76
摘要： PROBLEM TO BE SOLVED: To realize a fine structure and a high speed operation of a semiconductor device by a method wherein a narrow element isolation groove is filled with a silicon oxide film without voids.
SOLUTION: A silicon oxide film 2, a silicon nitride film 3, and a photoresist film 4 are formed on a wafer 1 as shown in (1) and (2) of Fig. 1 and a photoresist pattern 5 is formed. The nitride film 3 and the oxide film 2 are etched with the resist pattern 5 as a mask to form an aperture 6 and the resist pattern 5 is removed as shown in (3) and (4). The corners 7 of the nitride film 3 are removed by sputter etching in a high density plasma CVD device as shown in (5). A groove 8 having a depth of approximately 300 nm is formed in the wafer 1 by using the nitride film 3 as a mask and a thin silicon oxide film 9 is formed as shown in (6) and (7). Then the groove 8 is filled with a silicon oxide film. With such a constitution, as the dimensions of an element isolation region are reduced, a high speed operation and a fine structure of a semiconductor device can be realized.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了通过一种方法实现半导体器件的精细结构和高速操作，其中窄的元件隔离槽填充有无空隙的氧化硅膜。解决方案：如图1（1）和（2）所示，在晶片1上形成氧化硅膜2，氮化硅膜3和光刻胶膜4。形成光致抗蚀剂图案5。用抗蚀剂图案5作为掩模蚀刻氮化物膜3和氧化物膜2以形成孔6，并且如（3）和（4）所示去除抗蚀剂图案5。如（5）所示，通过溅射蚀刻在高密度等离子体CVD装置中除去氮化膜3的角部7。如（6）和（7）所示，通过使用氮化膜3作为掩模，在晶片1中形成深度约为300nm的槽8，形成薄的氧化硅膜9。然后，沟槽8被填充有氧化硅膜。利用这种结构，随着元件隔离区域的尺寸减小，可以实现半导体器件的高速操作和精细结构。

73. 发明专利

JP2001326269A SEMICONDUCTOR MANUFACTURING APPARATUS 失效
公开(公告)号：JP2001326269A
公开(公告)日：2001-11-22
申请号：JP2000147456
申请日：2000-05-15
申请人： HITACHI LTD
发明人： MIYA TAKESHI , HOSHINO MASAKAZU , OYAMA KATSUMI
IPC分类号： C23C16/44 , C23C16/511 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/68 , H01L21/683
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus which is little in deposition of particles to a semiconductor substrate and also in device damage. SOLUTION: A pusher pin is composed of a pin and a material covering around it, the material constituting the pin has a higher electric resistivity than that of the material covering around it and a top part of the pin directly contacting the semiconductor substrate is not covered but bared.

74. 发明专利

JP2001123271A METHOD OF PRECOATING PLASMA ENHANCED CVD SYSTEM 失效
公开(公告)号：JP2001123271A
公开(公告)日：2001-05-08
申请号：JP30201899
申请日：1999-10-25
申请人： HITACHI LTD
发明人： HOSHINO MASAKAZU , MIYA TAKESHI , HACHITANI MASAYUKI , OYAMA KATSUMI
IPC分类号： H01L21/205 , C23C16/44 , C23C16/511
摘要： PROBLEM TO BE SOLVED: To reduce the occurrence of foreign substance in a film deposition process in a plasma enhanced CVD system using microwave and radio frequency(RF) plasma and to attain a plasma enhanced CVD system having high working ratio. SOLUTION: After the completion of NF3 plasma cleaning, microwave is introduced into a reaction chamber 1 and RF is applied to an upper chamber 2 to precoat the internal wall surface of the reaction chamber 1 with an SiO2 film of desired thickness. Owing to the confinement of molecules adsorbed on the wall surface immediately after plasma cleaning and the smoothing of the wall surface, the increase of foreign substance due to peeled-off layer at film deposition and the occurrence of foreign substance by abnormal electric discharge at the internal wall surface of the reaction chamber 1 at film deposition can be prevented.

75. 发明专利

JP2003037103A Method for manufacturing semiconductor 审中-公开
标题翻译：制造半导体的方法
公开(公告)号：JP2003037103A
公开(公告)日：2003-02-07
申请号：JP2001225417
申请日：2001-07-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIGURO KOJI , SETOYAMA HIDETSUGU , OYAMA KATSUMI , MIYAUCHI AKIHIRO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide deposition with high aspect ratio to promote miniaturization.
SOLUTION: At a first manufacturing process, a film forming process in order to deposit an insulation layer 4 on a wafer 1 and a wiring 2, and etching treatment by sputter-etching with Ar+Ion extracted from a plasma 10 are performed at the same time. After a void 3 is formed between the wiring 2, the process moves on to an etching process of a second manufacturing process for a selective etching of the insulation layer 4 between the wiring 2 and the insulation layer 4 at the upper part of the wiring 2 to form an opening hole between the wiring 2 and to planarize the insulation layer at the upper part of the wiring 2. By repeating the first and second processes, the insulation layer 4 with high aspect ratio is embedded in the wiring 2 without generating voids.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供具有高纵横比的沉积以促进小型化。解决方案：在第一制造工艺中，为了将绝缘层4沉积在晶片1和布线2上的成膜工艺以及从等离子体10提取的用Ar +离子溅射蚀刻进行的蚀刻处理在相同时间。在布线2之后形成空隙3之后，进行到布线2的上部的布线2与绝缘层4之间的绝缘层4的选择性蚀刻的第二制造工序的蚀刻工序以在布线2之间形成开孔，并且在布线2的上部平坦化绝缘层。通过重复第一和第二处理，具有高纵横比的绝缘层4嵌入布线2中而不产生空隙。

76. 发明专利

JP2001176958A PLASMA PROCESSING METHOD 失效
公开(公告)号：JP2001176958A
公开(公告)日：2001-06-29
申请号：JP35549499
申请日：1999-12-15
申请人： HITACHI LTD
发明人： MIYA TAKESHI , HOSHINO MASAKAZU , HACHITANI MASAYUKI , OYAMA KATSUMI
IPC分类号： H01L21/302 , C23C16/505 , H01L21/3065 , H01L21/31 , H01L21/68 , H01L21/683 , H05H1/46
摘要： PROBLEM TO BE SOLVED: To provide a plasma processing method and a plasma processing system employing an electrostatic suction unit in which adhesion of particles to a semiconductor substrate is reduced. SOLUTION: In the plasma processing system employing an electrostatic suction unit 1, a semiconductor substrate 4 is charged negatively by applying a minus voltage to a suction electrode 2 which has been applied with a plus voltage before a plasma 5 disappears and then the plasma is extinguished.

77. 发明专利

JP2001172768A PLASMA CVD SYSTEM 失效
公开(公告)号：JP2001172768A
公开(公告)日：2001-06-26
申请号：JP35549599
申请日：1999-12-15
申请人： HITACHI LTD
发明人： HOSHINO MASAKAZU , MIYA TAKESHI , OYAMA KATSUMI , HACHITANI MASAYUKI
IPC分类号： H01L21/31 , C23C16/44 , C23C16/511
摘要： PROBLEM TO BE SOLVED: To provide a plasma CVD system having a high throughput by accelerating the cleaning rate of gaseous NF3 in a plasma CVD system. SOLUTION: By providing the upper part of a reaction chamber 1 confronted with an exhaust port 24 with a feed nozzle 23 of cleaning gas, reaction products such as SiF4 generated by the cleaning of films deposited on the wall face are swiftly exhausted, active F radicals or the like is fed to the vicinity of the wall face of an upper chamber 2, and by the reduction of the cleaning time by a high cleaning rate, a plasma CVD system having a high throughput can be realized.

78. 发明专利

JP2000173935A PLASMA TREATING DEVICE AND GAS-FEEDING METHOD 失效
公开(公告)号：JP2000173935A
公开(公告)日：2000-06-23
申请号：JP34958298
申请日：1998-12-09
申请人： HITACHI LTD
发明人： ISHIGURO KOJI , NAKAJIMA KATSUNORI , OYAMA KATSUMI , HACHITANI MASAYUKI , SHIDA HIROYUKI , SETOYAMA HIDETSUGU
IPC分类号： H01L21/302 , C23C14/34 , C23C16/44 , C23C16/455 , H01L21/205 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To reduce the number and the amount of foreign matters existing on the path from a gas bomb, which is introduced in a treating chamber along the flow of treatment gas to a gas introducing vent and the number and the amount of foreign matters in the vicinity of a gas-feed opening by a method wherein the flow rate at the gas feed opening in the treating chamber of the treatment gas is reduced. SOLUTION: In order to remove residual gas between valves 26, 29 and a massflow controller 27, an exhaust pump 15 is connected to an exhaust side via a change-over valve 30, and the timing when the valves 26, 29 and the controller 27 are opened is shifted. That is, after the opening of the valve 26 is completed, the valve 29 is opened with Δt1. A command that the controller 27 is gradually opened is sent from a CPU simultaneously with the time when the opening of the valve 29 is started, or in a time difference Δt2, and a voltage is applied to an electrostatic cluck electrode with a Δt3. At this time, at least either of the valves 26 and 29 is used as a valve of a variable valve travel and the inflow rate of treatment gas into a treating chamber 21 is reduced.

79. 发明专利

JP2001230242A PLASMA CVD DEVICE AND ITS GAS SUPPLY NOZZLE 失效
公开(公告)号：JP2001230242A
公开(公告)日：2001-08-24
申请号：JP2000040689
申请日：2000-02-18
申请人： HITACHI LTD
发明人： HOSHINO MASAKAZU , MIYA TAKESHI , HACHITANI MASAYUKI , OYAMA KATSUMI
IPC分类号： H01L21/31 , C23C16/44 , C23C16/511
摘要： PROBLEM TO BE SOLVED: To realize a gas supply nozzle generating less foreign matter when forming a film. SOLUTION: The gas supply nozzle 9 for introducing a film forming gas has an outer tube 23 and an inner tube 30. The tubes 23 and 30 have flanges at one ends. A plate 26 having low thermal conductivity is sandwiched between the flanges of the tubes 23 and 30, and the tubes 23, 30 and the plate 26 are mounted at the flange at a lower chamber 3 by bolts 27. Even when the tube 23 becomes a high temperature by colliding ions or the like to the outer surface of the tube 23 by sandwiching the plate 26, a temperature rise of the tube 30 can be prevented. An Ar gas flows to an air gap between the tubes 30 and 23, a pressure of the gap shows a low level from several value to 1,000 Pa, and the temperature rise of the tube 30 due to the thermal conduction is suppressed. As a result, since a temperature rise of SiH4 flowing in the tube 30 is low, and hence a reaction by-product due to the thermally decomposing reaction is not deposited in the tube 30.

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