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71. 发明申请

US20100065941A1 INTERMEDIATE SEMICONDUCTOR STRUCTURES 有权
标题翻译：中间半导体结构
公开(公告)号：US20100065941A1
公开(公告)日：2010-03-18
申请号：US12622939
申请日：2009-11-20
申请人： David H. Wells , H. Montgomery Manning
发明人： David H. Wells , H. Montgomery Manning
IPC分类号： H01L29/06
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/76283
摘要： An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
摘要翻译：公开了一种中间半导体结构，其包括衬底和形成在衬底中的至少一个底切结构。底切特征可以包括其中具有侧向空腔的垂直开口，垂直开口延伸到横向空腔下方。横向空腔可以包括刻面侧壁。

72. 发明申请

US20090286377A1 Methods of Forming Integrated Circuit Devices 有权
标题翻译：形成集成电路器件的方法
公开(公告)号：US20090286377A1
公开(公告)日：2009-11-19
申请号：US12512756
申请日：2009-07-30
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
摘要翻译：本发明包括形成半导体结构的方法和形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。在电极结构的外侧壁露出之后，去除保护盖。然后将电极结构并入电容器结构。

73. 发明申请

US20090176365A1 CONTACT FORMATION 有权
标题翻译：联系方式
公开(公告)号：US20090176365A1
公开(公告)日：2009-07-09
申请号：US12401996
申请日：2009-03-11
申请人： James Mathew , H. Montgomery Manning
发明人： James Mathew , H. Montgomery Manning
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.
摘要翻译：本公开包括各种方法，电路，设备和系统实施例。一种这样的方法实施例包括在绝缘体堆叠材料中形成沟槽，其具有位于多个栅极中的两个之间的沟槽的一部分，并且将间隔物材料沉积到沟槽的至少一个侧表面。该方法还包括将导电材料沉积到沟槽中并将盖材料沉积到沟槽中。

74. 发明申请

US20090173982A1 METHOD FOR FORMING MEMORY CELL AND DEVICE 有权
标题翻译：形成记忆细胞和装置的方法
公开(公告)号：US20090173982A1
公开(公告)日：2009-07-09
申请号：US12405574
申请日：2009-03-17
申请人： H. Montgomery Manning , David H. Wells
发明人： H. Montgomery Manning , David H. Wells
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译：存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

75. 发明授权

US07534694B2 Methods of forming a plurality of capacitors 失效
标题翻译：形成多个电容器的方法
公开(公告)号：US07534694B2
公开(公告)日：2009-05-19
申请号：US11477957
申请日：2006-06-28
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on a second pair of opposing sides by a different second capacitor electrode-forming material at the one elevation. Individual capacitor electrodes are formed within individual of the capacitor electrode openings. The capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成多个电容器的方法。在一个实施方案中，在衬底上形成多个电容器电极开口。电容器电极开口的个体在一个高度上由第一对电容器电极形成材料限定在第一对相对侧上，并且在一个高度处由不同的第二电容器电极形成材料限定在第二对相对侧上。单个电容器电极形成在电容器电极开口的单独内部。电容器电极被并入多个电容器中。考虑了其他方面和实现。

76. 发明授权

US07387939B2 Methods of forming semiconductor structures and capacitor devices 有权
标题翻译：形成半导体结构和电容器器件的方法
公开(公告)号：US07387939B2
公开(公告)日：2008-06-17
申请号：US10894633
申请日：2004-07-19
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
摘要翻译：本发明包括形成半导体结构的方法和形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。在电极结构的外侧壁露出之后，去除保护盖。然后将电极结构并入电容器结构。

77. 发明授权

US07306991B2 Stepped gate configuration for non-volatile memory 有权
标题翻译：非易失性存储器的步进门配置
公开(公告)号：US07306991B2
公开(公告)日：2007-12-11
申请号：US11257636
申请日：2005-10-25
申请人： H. Montgomery Manning , Kunal Parekh
发明人： H. Montgomery Manning , Kunal Parekh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.
摘要翻译：本文公开了具有带梯级栅极电介质的场效应晶体管及其制造方法的存储器件。阶梯式栅极电介质形成在半导体衬底上，由一对由栅极电介质隔开的电荷俘获电介质组成; 在其上形成栅极导体。源极和漏极区域形成在该对电荷俘获电介质的相对侧上的半导体衬底中。存储器件通过在半导体衬底上形成电荷俘获电介质层而制成。通过电荷捕获电介质层形成沟槽以暴露半导体衬底的一部分。栅极电介质层形成在沟槽内，栅极导体层形成在电荷俘获和栅极电介质层上。

78. 发明授权

US07271051B2 Methods of forming a plurality of capacitor devices 失效
标题翻译：形成多个电容器装置的方法
公开(公告)号：US07271051B2
公开(公告)日：2007-09-18
申请号：US11272232
申请日：2005-11-10
申请人： H. Montgomery Manning , Thomas M. Graettinger , Marsela Pontoh
发明人： H. Montgomery Manning , Thomas M. Graettinger , Marsela Pontoh
IPC分类号： H01L21/8234
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L27/10894 , H01L29/66181
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

79. 发明授权

US07157757B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07157757B2
公开(公告)日：2007-01-02
申请号：US11237396
申请日：2005-09-28
申请人： Kunal R. Parekh , H. Montgomery Manning
发明人： Kunal R. Parekh , H. Montgomery Manning
IPC分类号： H01L29/78
CPC分类号： H01L29/6653 , H01L21/28114 , H01L21/28238 , H01L21/823456 , H01L21/823468 , H01L29/66553 , H01L29/66583
摘要： The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.
摘要翻译：本发明包括半导体构造，形成栅极的方法以及形成晶体管结构的方法。本发明可以包括例如形成盖茨线的镶嵌方法。介电材料的薄段形成在介电材料的两个更厚的部分之间，其中较薄和较厚的电介质材料段在开口内。在开口内和电介质材料的较薄和较厚的部分之上形成栅栏材料。包含电介质材料的较薄和较厚部分上的栅极材料的结构可由具有限定水平方向的主表面的半导体衬底支撑。电介质材料的薄而较厚的部分可以包括基本上平行于衬底的主表面的上表面，并且可以在具有基本上垂直于衬底的主表面的主表面的台阶上彼此连接。

80. 发明授权

US07141511B2 Method and apparatus for fabricating a memory device with a dielectric etch stop layer 有权
公开(公告)号：US07141511B2
公开(公告)日：2006-11-28
申请号：US10832688
申请日：2004-04-27
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/461
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10885 , H01L27/10888 , H01L27/10894
摘要： The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

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