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71. 发明申请

US20060184747A1 Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory 有权
标题翻译：缓存目录的带宽通过将缓存目录分成两个较小的缓存目录，并为每个切片缓存目录复制侦听逻辑
公开(公告)号：US20060184747A1
公开(公告)日：2006-08-17
申请号：US11056721
申请日：2005-02-11
申请人： Guy Guthrie , William Starke , Derek Williams , Phillip Williams
发明人： Guy Guthrie , William Starke , Derek Williams , Phillip Williams
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0851
摘要： A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency matcher” may shift the cycle speed to a lower speed upon receiving snoop addresses from the interconnect thereby slowing down the rate at which requests are transmitted to the dispatch pipelines. Each dispatch pipeline is coupled to a sliced cache directory and is configured to search the cache directory to determine if data at the received addresses is stored in the cache memory. As a result of slowing down the rate at which requests are transmitted to the dispatch pipelines and accessing the two sliced cache directories simultaneously, the bandwidth or throughput of the cache directory may be improved.
摘要翻译：用于提高缓存目录的窥探带宽的缓存，系统和方法。高速缓存目录可以分成两个较小的缓存目录，每个具有自己的侦听逻辑。通过具有可以同时访问的两个缓存目录，带宽可以基本上加倍。此外，当从互连接收到窥探地址时，“频率匹配器”可以将周期速度转移到较低速度，从而将请求发送到调度管线的速率减慢。每个调度流水线被耦合到一个切片缓存目录，并被配置为搜索该高速缓存目录以确定该接收到的地址上的数据是否被存储在该高速缓冲存储器中。作为将请求发送到调度管线的速度变慢并且同时访问两个分片缓存目录的结果，可以提高缓存目录的带宽或吞吐量。

72. 发明申请

US20060179253A1 Data processing system, method and interconnect fabric that protect ownership transfer with a protection window extension 审中-公开
标题翻译：数据处理系统，方法和互连结构，通过保护窗口扩展来保护所有权转移
公开(公告)号：US20060179253A1
公开(公告)日：2006-08-10
申请号：US11054841
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016 , G06F2212/1048
摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.
摘要翻译：数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑响应于由多个窥探者提供的部分响应。多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

73. 发明申请

US20060179250A1 Data processing system and method for efficient L3 cache directory management 有权
公开(公告)号：US20060179250A1
公开(公告)日：2006-08-10
申请号：US11055301
申请日：2005-02-10
申请人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
发明人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

74. 发明申请

US20050003189A1 Thermoplastic powder material system for appearance models from 3D prinitng systems 有权
标题翻译：热塑性粉末材料系统，用于3D模型系统的外观模型
公开(公告)号：US20050003189A1
公开(公告)日：2005-01-06
申请号：US10848831
申请日：2004-05-19
申请人： James Bredt , Sarah Clark , Derek Williams , Matthew DiCologero
发明人： James Bredt , Sarah Clark , Derek Williams , Matthew DiCologero
IPC分类号： B32B5/16 , C08L101/00
CPC分类号： C08L101/00 , B29C64/165 , B33Y70/00 , Y10T428/25 , Y10T428/251 , Y10T428/252 , Y10T428/253 , Y10T428/254 , Y10T428/256 , Y10T428/257 , Y10T428/258 , Y10T428/259 , Y10T428/2982 , C08L2666/02
摘要： A materials system and method is provided to enable the formation of articles by three-dimensional printing. The materials system includes thermoplastic particulate filler material that allows the accurate definition of articles that are strong without being brittle.
摘要翻译：提供了一种能够通过三维打印形成物品的材料系统和方法。材料系统包括热塑性颗粒填料，其允许精确定义强而不易脆的制品。

75. 发明授权

US08756286B2 Alternate E-mail address configuration 有权
标题翻译：备用电子邮件地址配置
公开(公告)号：US08756286B2
公开(公告)日：2014-06-17
申请号：US12921762
申请日：2009-03-10
申请人： Len Albert Bayles , Ernie Dainow , Derek Williams , Joseph Chiu Kit Yee
发明人： Len Albert Bayles , Ernie Dainow , Derek Williams , Joseph Chiu Kit Yee
IPC分类号： G06F15/16
CPC分类号： H04L29/12594 , H04L51/066 , H04L51/14 , H04L51/28 , H04L61/3035 , H04L61/307
摘要： A method is provided for transmitting an electronic mail (e-mail) message from a sender having a non-ASCII e-mail address to a recipient. Provided is an e-mail directory associated with a requested primary e-mail address, having a non-ASCII form, and a corresponding alternate e-mail address having an ASCII form. The alternate e-mail is generated from the primary e-mail address using a reversible encoding scheme having a one-to-one relationship. The e-mail message, the alternate e-mail address, and the primary e-mail address are transmitted to the recipient via a plurality of mail delivery elements. The alternate e-mail address is transmitted to a mail delivery element incapable of processing non-ASCII characters. The alternate e-mail address is for use by the mail delivery element to identify the sender and deliver the e-mail message to the recipient for display.
摘要翻译：提供一种用于从具有非ASCII电子邮件地址的发送方向接收者发送电子邮件（电子邮件）消息的方法。提供了与所请求的主电子邮件地址相关联的电子邮件目录，具有非ASCII格式以及具有ASCII格式的对应备用电子邮件地址。使用具有一对一关系的可逆编码方案，从主电子邮件地址生成备用电子邮件。电子邮件消息，备用电子邮件地址和主要电子邮件地址通过多个邮件传递元件发送给接收者。备用电子邮件地址被传送到不能处理非ASCII字符的邮件传递元件。备用电子邮件地址由邮件传递元件用于识别发件人，并将电子邮件传送给收件人进行显示。

76. 发明申请

US20070168618A1 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US20070168618A1
公开(公告)日：2007-07-19
申请号：US11333615
申请日：2006-01-17
申请人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

77. 发明申请

US20070083717A1 Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response 失效
标题翻译：链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行进行顺序同步访问
公开(公告)号：US20070083717A1
公开(公告)日：2007-04-12
申请号：US11245313
申请日：2005-10-06
申请人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
发明人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822
摘要： A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.
摘要翻译：一种方法和数据处理系统，用于在数据在链中的第一处理器的高速缓存中接收之前，将链接中的高速缓存行的连续的均匀处理器请求顺序耦合。分配链接的中间一致性状态，以便在启动链路的第一个处理器接收到数据之前跟踪处理器请求链和后续访问权限。所分配的链接中间一致性状态标识处理器操作，并且方向标识符标识要向其转发高速缓存行的处理器。当在链中的第一处理器的高速缓存处接收数据时，第一处理器完成其数据处理（或与数据）的操作，然后将数据转发到链中的下一个处理器。当最后一个链接处理器窥探非均匀操作时，链条立即停止。

78. 发明申请

US20060277370A1 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
公开(公告)号：US20060277370A1
公开(公告)日：2006-12-07
申请号：US11146443
申请日：2005-06-06
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

79. 发明申请

US20060271742A1 Data processing system, cache system and method for actively scrubbing a domain indication 失效
公开(公告)号：US20060271742A1
公开(公告)日：2006-11-30
申请号：US11136651
申请日：2005-05-24
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.

80. 发明申请

US20060184748A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
公开(公告)号：US20060184748A1
公开(公告)日：2006-08-17
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

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