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71. 发明申请

US20120044770A1 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS NOR闪存阵列，以及形成基于NAND的NMOS闪存阵列的方法
公开(公告)号：US20120044770A1
公开(公告)日：2012-02-23
申请号：US13317678
申请日：2011-10-25
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器或可重构逻辑器件具有NOR闪存非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过当电荷保持晶体管未被选择用于读取时的电荷保持晶体管。最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

72. 发明申请

US20090310405A1 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/-10v BVDS 失效
标题翻译：行解码器和选择门解码器结构，适用于低于+/- 10v BVDS的基于闪存的EEPROM
公开(公告)号：US20090310405A1
公开(公告)日：2009-12-17
申请号：US12456354
申请日：2009-06-16
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/06 , G11C16/04 , G11C8/00 , G11C7/00 , G11C5/14
CPC分类号： G11C16/12 , G11C16/08 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
摘要翻译：非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管非易失性存储单元。产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

73. 发明申请

US20050141298A1 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US20050141298A1
公开(公告)日：2005-06-30
申请号：US11011306
申请日：2004-12-14
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , G11C16/14 , H01L21/8247 , H01L27/115 , G11C5/00
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

74. 发明申请

US20050128805A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US20050128805A1
公开(公告)日：2005-06-16
申请号：US11036961
申请日：2005-01-14
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

75. 发明授权

US06381670B1 Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation 失效
标题翻译：闪存阵列具有最大和最小阈值电压检测，用于消除过度擦除问题并增强写入操作
公开(公告)号：US06381670B1
公开(公告)日：2002-04-30
申请号：US08823571
申请日：1997-03-25
申请人： Peter Wung Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Wen-Tan Fan
发明人： Peter Wung Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Wen-Tan Fan
IPC分类号： G06F1216
CPC分类号： G11C16/3418 , G11C8/10 , G11C8/12 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3431
摘要： A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.
摘要翻译：已经消除了擦除了单元的闪存，并且包括可调节的擦除和编程条件。在整个擦除和编程操作期间测量单元的最大和最小阈值电压。通过施加低于先前测量的最小阈值电压的字线电压来关闭过擦除的电池。消除了被擦除的单元的预编程和修复操作。实现了低读取电压。栅极，源极，漏极电压，脉冲宽度和脉冲数的擦除和编程条件可根据阈值电压进行调节，以优化性能。查找表存储相关的门，源，漏极电压，脉冲的宽度和相对于可调整条件的阈值电压的脉冲数。闪存运行所带来的好处包括高效率，长寿命，窄阈值电压分配，低功耗，低工艺敏感性。

76. 发明授权

US5978277A Bias condition and X-decoder circuit of flash memory array 失效
标题翻译：闪存阵列的偏置条件和X解码器电路
公开(公告)号：US5978277A
公开(公告)日：1999-11-02
申请号：US159793
申请日：1998-09-24
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter Wung Lee
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter Wung Lee
IPC分类号： G11C16/08 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/08
摘要： New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well. Separated X-decoder wells are constructed to provide voltages to the word lines of memory blocks. Every word line in a memory block has an X-decoder driver so that the word line can be erased or repaired individually. A new layout is also presented for the construction of the X-decoder circuits.
摘要翻译：闪存单元和X解码器电路的新偏置条件用于提供偏置条件。在擦除操作中，向体积提供正高电压，并且向控制栅极提供负的高电压以建立足够的电场以诱发电子隧道效应。在修复电池的阈值电压的操作中，偏置的电压被反转。提出了第一个X解码器电路结构，用于向存储器单元提供正和负高电压用于块擦除或修复。第一X解码器电路结构具有多个X解码器块，每个X解码器块分别构造在分离的X解码器阱中，并且存储单元制造在单独的公共阵列井中。呈现第二X解码器电路结构以提供用于擦除或修复小扇区字线的适当偏置条件。对于第二X解码器电路结构，每个存储器块以分离的阵列阱制造。分离的X解码器阱被构造成向存储器块的字线提供电压。存储块中的每个字线都有一个X解码器驱动程序，以便字线可以单独擦除或修复。还介绍了X解码器电路结构的新布局。

77. 发明授权

US08295087B2 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS 失效
标题翻译：行解码器和选择栅极解码器结构，适用于低于+/- 10v BVDS的基于闪存的EEPROM
公开(公告)号：US08295087B2
公开(公告)日：2012-10-23
申请号：US12456354
申请日：2009-06-16
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C11/4193
CPC分类号： G11C16/12 , G11C16/08 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
摘要翻译：非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管非易失性存储单元。产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

78. 发明申请

US20090310411A1 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS 失效
标题翻译：行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
公开(公告)号：US20090310411A1
公开(公告)日：2009-12-17
申请号：US12455936
申请日：2009-06-09
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C7/00 , G11C16/16 , G11C16/06 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

79. 发明申请

US20090279360A1 NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS或闪速存储器阵列，以及形成基于NAND的NMOS NOR闪存阵列
公开(公告)号：US20090279360A1
公开(公告)日：2009-11-12
申请号：US12387771
申请日：2009-05-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C16/06 , H01L21/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR闪存非易失性存储器电路阵列。每个NOR非易失性存储器电路包括以NAND串串联连接的多个电荷保持晶体管。最高电荷保持晶体管的漏极连接到与串联连接的电荷保持晶体管相关联的位线，并且最下面的电荷保持晶体管的源极连接到与电荷保持晶体管相关联的源极线。每行上的电荷保持晶体管的每个控制栅极共同连接到字线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

80. 发明申请

US20070133341A1 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US20070133341A1
公开(公告)日：2007-06-14
申请号：US11633334
申请日：2006-12-04
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

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