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71. 发明申请

US20130249015A1 SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES 有权
公开(公告)号：US20130249015A1
公开(公告)日：2013-09-26
申请号：US13893026
申请日：2013-05-13
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

72. 发明申请

US20130178027A1 NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION 有权
标题翻译：非易失性存储器（NVM）和逻辑集成
公开(公告)号：US20130178027A1
公开(公告)日：2013-07-11
申请号：US13780574
申请日：2013-02-28
申请人： Mark D. Hall , Frank K. Baker, JR. , Mehul D. Shroff
发明人： Mark D. Hall , Frank K. Baker, JR. , Mehul D. Shroff
IPC分类号： H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/42348 , H01L29/4933 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66833 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
摘要翻译：形成NVM单元和逻辑晶体管的方法使用半导体衬底。在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。

73. 发明授权

US08389365B2 Non-volatile memory and logic circuit process integration 有权
标题翻译：非易失性存储器和逻辑电路工艺集成
公开(公告)号：US08389365B2
公开(公告)日：2013-03-05
申请号：US13077501
申请日：2011-03-31
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/823842 , H01L21/823857 , H01L27/11536 , H01L29/66825
摘要： A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.
摘要翻译：公开了一种用于形成用于非易失性存储单元晶体管的集成电路的方法，其包括：在所述衬底的第一区域和所述衬底的第二区域中的衬底上形成离散存储元件层; 在所述第一区域和所述第二区域中的离散存储元件层上形成第一介电材料层; 在所述第一区域和所述第二区域中的所述第一介电材料层上形成阻挡功函数材料的第一层; 以及从所述第二区域去除所述第一层屏障功能材料，从所述第二区域去除所述第一介电材料层，以及从所述第二区域移除所述离散存储元件层。在去除之后，在第一区域和第二区域中的衬底上形成第二层屏障功能材料层。从第一区域去除第二层屏障功能材料。存储器件的第一栅极形成在第一区域中。第一栅极包括第一层屏障功能材料的一部分。存储器件包括电荷存储结构，其包括离散存储元件层的一部分。晶体管的第二栅极形成在第二区域中，第二栅极包括第二层屏障功能材料的一部分。

74. 发明授权

US08318576B2 Decoupling capacitors recessed in shallow trench isolation 有权
标题翻译：去耦电容器凹入浅沟槽隔离
公开(公告)号：US08318576B2
公开(公告)日：2012-11-27
申请号：US13092046
申请日：2011-04-21
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L27/0629 , H01L29/66181
摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.
摘要翻译：一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板通过STI区域并且通过侧壁电介质层与串扰隔离。

75. 发明授权

US08304331B2 Angled ion implantation in a semiconductor device 有权
标题翻译：半导体器件中的角度离子注入
公开(公告)号：US08304331B2
公开(公告)日：2012-11-06
申请号：US12787101
申请日：2010-05-25
申请人： Mark D. Hall
发明人： Mark D. Hall
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L27/11521 , H01L27/11568 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.
摘要翻译：角度离子注入用于在形成在掩模开口中的半导体柱中形成掺杂区域。支柱形成为小于面罩高度的高度。角度离子注入可用于形成半导体器件的区域，例如半导体器件实体的半导体器件的主体连接区域，晕圈区域或电流端子延伸区域。

76. 发明申请

US20120267759A1 DECOUPLING CAPACITORS RECESSED IN SHALLOW TRENCH ISOLATION 有权
标题翻译：解冻电容器在低温分离器中进行
公开(公告)号：US20120267759A1
公开(公告)日：2012-10-25
申请号：US13092046
申请日：2011-04-21
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/945 , H01L27/0629 , H01L29/66181
摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.
摘要翻译：一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板通过STI区域并且通过侧壁电介质层与串扰隔离。

77. 发明申请

US20120267758A1 Isolated Capacitors Within Shallow Trench Isolation 有权
标题翻译：隔离电容器在浅沟槽隔离
公开(公告)号：US20120267758A1
公开(公告)日：2012-10-25
申请号：US13092037
申请日：2011-04-21
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/945 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).
摘要翻译：半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层（10）中的底部电容器板，电容器电介质层（22）和凹陷顶部电容器板（28），其被STI区域（30）覆盖并且由侧壁电介质层（23）与串扰隔离。

78. 发明授权

US08236638B2 Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner 有权
标题翻译：浅沟槽隔离用于结合侧墙和底衬的SOI结构
公开(公告)号：US08236638B2
公开(公告)日：2012-08-07
申请号：US11788184
申请日：2007-04-18
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210）其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

79. 发明申请

US20110294292A1 METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成共享接触的方法
公开(公告)号：US20110294292A1
公开(公告)日：2011-12-01
申请号：US12787296
申请日：2010-05-25
申请人： Olubunmi O. Adetutu , Ted R. White , Mark D. Hall
发明人： Olubunmi O. Adetutu , Ted R. White , Mark D. Hall
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/76807 , H01L21/76808
摘要： A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.
摘要翻译：提供一种用于在具有对应于第一晶体管的栅电极和对应于第二晶体管的源/漏区的半导体器件中形成共用触点的方法。该方法包括在覆盖栅电极和源极/漏极区的电介质层中形成第一开口，其中第一开口基本上延伸到对应于第一晶体管的栅电极。该方法还包括在形成第一开口之后，在覆盖介质层中形成与第一开口邻接的第二开口，其中第二开口基本上延伸到对应于第二晶体管的源极/漏极区域。该方法还包括通过用导电材料填充第一开口和第二开口来形成对应于第一晶体管的栅电极与对应于第二晶体管的源极/漏极区之间的共用接触。

80. 发明申请

US20090108296A1 SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES 有权
标题翻译：具有不同介质厚度的半导体器件
公开(公告)号：US20090108296A1
公开(公告)日：2009-04-30
申请号：US11931565
申请日：2007-10-31
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译：具有具有不同厚度的电介质层的器件的集成电路。电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。硅层位于包含锗或碳的层之上。

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