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71. 发明授权

US07859081B2 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US07859081B2
公开(公告)日：2010-12-28
申请号：US11731543
申请日：2007-03-29
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

72. 发明授权

US07288752B2 CMOS radiation-measuring circuit with a variable threshold 有权
标题翻译：具有可变阈值的CMOS辐射测量电路
公开(公告)号：US07288752B2
公开(公告)日：2007-10-30
申请号：US10620829
申请日：2003-07-16
申请人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
IPC分类号： G01J1/44 , H03K17/78
CPC分类号： G01T1/026 , H01L27/144
摘要： A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.
摘要翻译：辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。

73. 发明授权

US06825687B2 Selective cooling of an integrated circuit for minimizing power loss 有权
标题翻译：集成电路的选择性冷却，以最大限度地减少功率损耗
公开(公告)号：US06825687B2
公开(公告)日：2004-11-30
申请号：US10230466
申请日：2002-08-29
申请人： Ali Keshavarzi , Jaume A. Segura , Siva G. Narendra , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Siva G. Narendra , Vivek K. De
IPC分类号： H03K1716
CPC分类号： H03K19/0016 , H01L27/0251
摘要： An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.
摘要翻译：一种用于降低在集成电路中使用的晶体管的泄漏电流的装置和方法，其选择性地将集成电路中的处理器电路切换到待机状态。包括冷却装置并且选择性地位于集成电路的紧邻用于在主动状态和待机状态之间切换处理器电路的晶体管的区域中。冷却装置冷却晶体管，以改善其泄漏和有功电流状态，从而提高晶体管的效率并减少其漏电流。

74. 发明授权

US06232827B1 Transistors providing desired threshold voltage and reduced short channel effects with forward body bias 失效
标题翻译：晶体管提供期望的阈值电压和减少的短通道效应与前向偏置
公开(公告)号：US06232827B1
公开(公告)日：2001-05-15
申请号：US09078388
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.
摘要翻译：在一个实施例中，半导体电路包括具有主体的第一组场效应晶体管和包括净通道掺杂水平DL1的参数。该电路还包括导体，用于向主体提供第一电压以使第一组晶体管偏置，第一组晶体管在正向偏置时具有正向偏置阈值电压（VtFBB），其中DL1至少为25 高于第一组晶体管中的净通道掺杂水平，其将导致零体偏置阈值电压等于VtFBB，其中除了净通道掺杂水平之外的参数不变。在另一实施例中，半导体电路包括第一电路，其包括具有主体的第一组场效应晶体管。电路还包括第一电压源，以向主体提供第一电压，使得场效应晶体管具有正向体偏置，第一电压处于导致电路经历软错误故障率降低的水平，与当电路没有正向偏置时。

75. 发明授权

US06828638B2 Decoupling capacitors for thin gate oxides 有权
标题翻译：薄栅氧化物去耦电容器
公开(公告)号：US06828638B2
公开(公告)日：2004-12-07
申请号：US09469406
申请日：1999-12-22
申请人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
发明人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
IPC分类号： H01L2976
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

76. 发明授权

US06411156B1 Employing transistor body bias in controlling chip parameters 有权
标题翻译：采用晶体管体偏置来控制芯片参数
公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译：在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号控制电路。在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

77. 发明授权

US06300819B1 Circuit including forward body bias from supply voltage and ground nodes 失效
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

78. 发明授权

US06218892B1 Differential circuits employing forward body bias 失效
标题翻译：采用正向偏置的差分电路
公开(公告)号：US06218892B1
公开(公告)日：2001-04-17
申请号：US09256842
申请日：1999-02-24
申请人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
发明人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0812 , H03L7/0995
摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.
摘要翻译：在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

79. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

80. 发明授权

US06734498B2 Insulated channel field effect transistor with an electric field terminal region 有权
公开(公告)号：US06734498B2
公开(公告)日：2004-05-11
申请号：US09165483
申请日：1998-10-02
申请人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
发明人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
IPC分类号： H01L2701
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/78606 , H01L29/78645 , H01L29/78648
摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

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