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71. 发明授权

US5510740A Method for synchronizing clocks upon reset 失效
标题翻译：复位时同步时钟的方法
公开(公告)号：US5510740A
公开(公告)日：1996-04-23
申请号：US272879
申请日：1994-07-11
申请人： Robert Farrell , Sharad Mehrotra
发明人： Robert Farrell , Sharad Mehrotra
IPC分类号： H03K5/135 , H03K5/13
CPC分类号： H03K5/135
摘要： A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.
摘要翻译：同步时钟电路接收时钟信号，并且根据所接收的时钟信号，在复位时提供相对于所接收的时钟信号具有已知相位关系的分频时钟信号。为了提供已知的相位关系，并且因此使接收到的时钟信号和分频时钟信号同步，可选地跳过分频下降时钟信号的周期。复位信号被调节并应用于主动边沿检测器。根据主动边沿检测器可选择地跳过分频下降时钟的周期。

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