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71. 发明授权

US06963248B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US06963248B2
公开(公告)日：2005-11-08
申请号：US10783563
申请日：2004-02-23
申请人： Christopher M. Ward , Pieter Vorenkamp
发明人： Christopher M. Ward , Pieter Vorenkamp
IPC分类号： H01F17/00 , H01L27/08 , H03B5/12 , H03B5/36 , H03H11/12 , H03J1/00 , H03J3/04 , H03J3/08 , H03J3/18 , H03L7/06 , H03B5/32
CPC分类号： H03J3/185 , H01F17/0006 , H01F2017/0053 , H01F2021/125 , H01L27/08 , H03B5/364 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J2200/10
摘要： A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.
摘要翻译：周期性信号发生电路包括适于集成在半导体衬底上的差分晶体振荡器。振荡器利用外部晶体作为谐振器。电路被设计成使得谐振器引线上存在差分正弦信号以提供干扰信号的优异的噪声抑制。在整个振荡器中保持差分信号传输以抑制由衬底上可能存在的其它电路产生的噪声。由于产生了受控正弦波幅度和低谐波含量的差分信号，因此通过电源，基板，接合线和焊盘从振荡器辐射的噪声被减小。振荡器产生低相位噪声，使振荡器可用于对失真敏感的应用中，如电视接收机。该电路是具有低抖动的方波，从而减少数字电路产生的抖动，这将会利用该方波时钟信号。

72. 发明申请

US20050134363A1 Reference ladder having improved feedback stability 有权
公开(公告)号：US20050134363A1
公开(公告)日：2005-06-23
申请号：US11056198
申请日：2005-02-14
申请人： Pieter Vorenkamp
发明人： Pieter Vorenkamp
IPC分类号： H03M1/06 , H03M1/36
CPC分类号： H03M1/0602 , H03M1/365
摘要： A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks. An alternate embodiment includes first and second resistor ladders that are configured to generate substantially identical voltages across their respective taps. First and second feedback networks sense voltages on the first resistor ladder and control current sources that drive both the first resistor ladder and the second resistor ladder. Differential input stages that are connected to the taps of the second resistor ladder and are at least partially isolated from the feedback networks that are connected to the first resistor ladder, thereby improving stability of the feedback networks.

73. 发明授权

US06903588B2 Slew rate controlled output buffer 有权
标题翻译：压摆率控制输出缓冲器
公开(公告)号：US06903588B2
公开(公告)日：2005-06-07
申请号：US10413519
申请日：2003-04-15
申请人： Pieter Vorenkamp
发明人： Pieter Vorenkamp
IPC分类号： H03K19/003 , H03K5/12
CPC分类号： H03K19/00361
摘要： An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.
摘要翻译：输出缓冲器包括耦合在输入和输出端子之间的第一和第二电路部分。每个电路部分包括电容元件; 具有耦合到所述电容元件的栅极的输出晶体管和驱动所述输出端子处的电压的漏极; 以及电流发生器，其被配置为响应于所述输入端子处的逻辑转换而产生针对所述电容元件的充电电流，其中所述充电电流在所述输出晶体管的栅极处形成基本线性的斜坡电压，由此所述斜坡电压控制输出端电压的转换速率。

74. 发明授权

US06885236B2 Reference ladder having improved feedback stability 有权
标题翻译：参考梯具有改进的反馈稳定性
公开(公告)号：US06885236B2
公开(公告)日：2005-04-26
申请号：US10283088
申请日：2002-10-30
申请人： Pieter Vorenkamp
发明人： Pieter Vorenkamp
IPC分类号： H03M1/06 , H03M1/36 , H03M1/34 , G05F1/46
CPC分类号： H03M1/0602 , H03M1/365
摘要： A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks. An alternate embodiment includes first and second resistor ladders that are configured to generate substantially identical voltages across their respective taps. First and second feedback networks sense voltages on the first resistor ladder and control current sources that drive both the first resistor ladder and the second resistor ladder. Differential input stages that are connected to the taps of the second resistor ladder and are at least partially isolated from the feedback networks that are connected to the first resistor ladder, thereby improving stability of the feedback networks.
摘要翻译：参考梯形图被配置为具有改进的反馈稳定性。参考梯形电路包括具有产生多个参考电压的多个抽头的电阻梯。电阻梯由多个抽头中的第一抽头的第一电流源和多个抽头的第二抽头处的第二电流源驱动。第一反馈网络感测在第一抽头处的电压，并且基于第一感测电压来控制第一电流源。第二反馈网络感测第二抽头处的电压，并且基于第二感测电压来控制第二电流源。第一和第二抽头各自用作电阻梯的力抽头和感测抽头。通过收敛力和感测抽头，连接到多个抽头的差分输入级至少部分地与反馈网络隔离，从而提高反馈网络的稳定性。替代实施例包括被配置为在它们各自的抽头上产生基本上相同的电压的第一和第二电阻器梯形。第一和第二反馈网络检测第一电阻梯的电压和驱动第一电阻梯和第二电阻梯的控制电流源。差分输入级连接到第二电阻梯的抽头并且至少部分地与连接到第一电阻梯的反馈网络隔离，从而提高反馈网络的稳定性。

75. 发明授权

US06865381B2 System and method for on-chip filter tuning 有权
公开(公告)号：US06865381B2
公开(公告)日：2005-03-08
申请号：US10388398
申请日：2003-03-17
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr
IPC分类号： H01F17/00 , H01L23/522 , H01L27/02 , H01L27/08 , H03B5/12 , H03B5/36 , H03D3/18 , H03D7/16 , H03D7/18 , H03G1/00 , H03H11/12 , H03J1/00 , H03J3/04 , H03J3/08 , H03J3/18 , H03L7/10 , H03L7/23 , H04B1/00
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

76. 发明授权

US5298801A Track-and-hold circuit 失效
标题翻译：跟踪保持电路
公开(公告)号：US5298801A
公开(公告)日：1994-03-29
申请号：US938921
申请日：1992-08-31
申请人： Pieter Vorenkamp , Johannes P. M. Verdaasdonk
发明人： Pieter Vorenkamp , Johannes P. M. Verdaasdonk
IPC分类号： G11C27/02 , H03K17/00 , H03K17/60
CPC分类号： G11C27/026
摘要： A track-and-hold circuit includes an input stage (IS), an output stage (OS) and a switching stage (SS). The switching stage is coupled between the input stage and the output stage. The switching stage includes a switching transistor (T10), a differential amplifier (T11/T12), a current source (T13/R11), and a capacitor (C11). In order to improve the frequency response, the input stage is provided with a passive impedance coupled between a base of the switching transistor and a first supply terminal (1) and the input stage is adapted to supply a signal current to the base of the switching transistor. This signal current is related to an input signal applied to the input stage. The output stage includes a first output transistor (T14), a first current source (T15) switched by a tracking signal (Vt), a second output transistor (T16), and a second current source.
摘要翻译：轨道保持电路包括输入级（IS），输出级（OS）和开关级（SS）。开关级耦合在输入级和输出级之间。开关级包括开关晶体管（T10），差分放大器（T11 / T12），电流源（T13 / R11）和电容器（C11）。为了提高频率响应，输入级被提供有耦合在开关晶体管的基极与第一电源端（1）之间的无源阻抗，并且输入级适于向开关的基极提供信号电流晶体管。该信号电流与施加到输入级的输入信号有关。输出级包括第一输出晶体管（T14），由跟踪信号（Vt）切换的第一电流源（T15），第二输出晶体管（T16）和第二电流源。

77. 发明申请

US20210224078A1 Systems and Methods for Generating Wake Signals from Known Users 有权
公开(公告)号：US20210224078A1
公开(公告)日：2021-07-22
申请号：US17151152
申请日：2021-01-16
申请人： Kurt F. Busch , Jeremiah H. Holleman, III , Pieter Vorenkamp , Stephen W. Bailey , David Christopher Garrett
发明人： Kurt F. Busch , Jeremiah H. Holleman, III , Pieter Vorenkamp , Stephen W. Bailey , David Christopher Garrett
IPC分类号： G06F9/4401 , G06F16/22 , G06N3/08 , G06N3/04
摘要： Provided herein is an integrated circuit including, in some embodiments, a host processor, a digitally implemented neural network co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor can be operable as a stand-alone processor. The neural network co-processor may include a digitally implemented neural network. The co-processor is configured to enhance special-purpose processing of the host processor through an artificial neural network. In such embodiments, the host processor is wake keyword identifier processor configured to transmit one or more detected patterns to the co-processor over a communications interface. The co-processor is configured to transmit the recognized patterns to the host processor which can then identify and verify wake keywords spoken by a known user.

78. 发明授权

US09548251B2 Semiconductor interposer having a cavity for intra-interposer die 有权
标题翻译：具有用于内插器模腔的腔室的半导体插入器
公开(公告)号：US09548251B2
公开(公告)日：2017-01-17
申请号：US13349045
申请日：2012-01-12
申请人： Rezaur Rahman Khan , Sam Ziqun Zhao , Pieter Vorenkamp , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Xiangdong Chen
发明人： Rezaur Rahman Khan , Sam Ziqun Zhao , Pieter Vorenkamp , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Xiangdong Chen
IPC分类号： H01L23/48 , H01L23/13 , H01L25/065 , H01L23/498
CPC分类号： H01L23/13 , H01L23/49827 , H01L23/49833 , H01L25/0657 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2924/15151 , H01L2924/15153 , H01L2924/15311 , H01L2924/157
摘要： A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.
摘要翻译：半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。半导体插入器位于衬底上。插入式管芯设置在半导体插入器的空腔内。导热粘合剂设置在空腔内并与内插器模具接触。此外，顶部管芯位于半导体插入器上方。在一个实现中，半导体插入器是硅插入器。在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

79. 发明授权

US08193772B2 Overvoltage protection utilized when a battery is removed from a system 失效
标题翻译：当电池从系统中取出时，使用过电压保护
公开(公告)号：US08193772B2
公开(公告)日：2012-06-05
申请号：US12060675
申请日：2008-04-01
申请人： Russell Eliot Radke , Jay Edward Ackerman , Pieter Vorenkamp
发明人： Russell Eliot Radke , Jay Edward Ackerman , Pieter Vorenkamp
IPC分类号： H02J7/00
CPC分类号： H02J7/0029
摘要： A system and method are provided for safely recharging a battery. A current source is coupled to a node and configured to produce a current. The battery is coupled to the node, and is configured to recharge during a recharging cycle based on receiving the current through the node. An overvoltage protection system is coupled between the node and the current source, and configured to disable the current source when a voltage at the node exceeds a threshold value. For example, the current source may be substantially instantaneously disabled when this occurs.
摘要翻译：提供了一种用于安全地对电池充电的系统和方法。电流源耦合到节点并被配置为产生电流。电池耦合到节点，并且被配置为在充电循环期间基于接收通过节点的电流进行充电。过电压保护系统耦合在节点和电流源之间，并且被配置为当节点处的电压超过阈值时禁用电流源。例如，当发生这种情况时，电流源可以基本上被瞬时禁用。

80. 发明授权

US08164501B2 Method and system for time interleaved digital to analog conversion for a cable modem 有权
标题翻译：用于电缆调制解调器的时间交织数模转换的方法和系统
公开(公告)号：US08164501B2
公开(公告)日：2012-04-24
申请号：US10975106
申请日：2004-10-28
申请人： Arnoldus G. Venes , Kevin L. Miller , Pieter Vorenkamp
发明人： Arnoldus G. Venes , Kevin L. Miller , Pieter Vorenkamp
IPC分类号： H03M1/66
CPC分类号： H04N21/6118 , H04N7/17309 , H04N21/6168
摘要： Provided is a transmitter in a communications system including a plurality of digital to analog converters. Also included is a plurality of clocks, each being communicably coupled to a corresponding one of the digital to analog converters.
摘要翻译：提供了一种包括多个数模转换器的通信系统中的发射机。还包括多个时钟，每个时钟可通信地耦合到数模转换器中相应的一个。

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