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    • 75. 发明申请
    • Anti-aliased tagging using look-up table edge pixel identification
    • 使用查找表边缘像素识别的抗锯齿标签
    • US20070146386A1
    • 2007-06-28
    • US11317782
    • 2005-12-23
    • Robert LoceBeilei XuStuart SchweidSon NguyenMichael Branciforte
    • Robert LoceBeilei XuStuart SchweidSon NguyenMichael Branciforte
    • G09G5/00
    • G06T11/203
    • The teachings provided herein disclose an image processing method for rendering a digital image possessing anti-aliased pixels by selecting a target pixel location within the digital image; observing a set of pixels within a pixel observation window superimposed on the digital image relative to the target pixel location; generating edge-state codes for a plurality of pairs of neighboring vectors of pixels within the pixel observation window; generating edge-identification codes from the plurality of edge-state codes using at least one look-up table; and, utilizing the edge-identification codes to select and apply to the digital image at the target pixel either anti-aliased rendering or conventional halftoning. The anti-aliasing may employ pixel signals that are high addressable and directionally biased to a particular orientation.
    • 本文提供的教导公开了一种图像处理方法,用于通过选择数字图像内的目标像素位置来渲染具有抗锯齿像素的数字图像; 观察相对于目标像素位置叠加在数字图像上的像素观察窗内的一组像素; 为所述像素观察窗口内的多个相邻像素向量对生成边缘状态代码; 使用至少一个查找表从所述多个边缘状态代码生成边缘识别码; 并且利用边缘识别码选择并应用于目标像素处的数字图像,即抗锯齿渲染或常规半色调。 抗混叠可以采用高可寻址性并且被定向偏置于特定取向的像素信号。
    • 80. 发明授权
    • Placement and routing of circuits using a combined processing/buffer cell
    • 使用组合处理/缓冲单元的电路布局和布线
    • US06714903B1
    • 2004-03-30
    • US09113995
    • 1998-07-10
    • Wei-Mun ChuSudhakar R. GouravaramSon Nguyen
    • Wei-Mun ChuSudhakar R. GouravaramSon Nguyen
    • G06F1710
    • G06F17/5068G06F17/505
    • A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells. According to this aspect of the invention, one of the cells obtained from the cell library, referred to as a combined cell, includes (1) a signal processing circuit; (2) a buffer circuit for buffering a signal external to the integrated circuit in which the combined cell is to be included; and (3) layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
    • 用于包含在用于设计集成电路的单元库中的单元。 该单元包括信号处理电路和缓冲电路,用于缓冲其中要包括单元的集成电路的外部信号。 单元还包括用于指定信号处理电路和缓冲电路之间的互连迹线的布局的布局信息。 本发明还涉及一种用于在设计集成电路的设计期间执行布局和布线的方法,其中从单元库获得单元,所获得的单元布置在集成电路管芯上,互连在单元之间布线。 根据本发明的这个方面,从被称为组合单元的单元库获得的单元之一包括(1)信号处理电路; (2)用于缓冲集成电路外部的信号的缓冲电路,其中组合的单元将被包括在该集成电路中; 以及(3)用于指定信号处理电路和缓冲电路之间的互连迹线的布局的布局信息。