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    • 73. 发明授权
    • High frequency resonator, and manufacturing method therefor
    • 高频谐振器及其制造方法
    • US06259189B1
    • 2001-07-10
    • US09337279
    • 1999-06-22
    • Nak Cheol SungMin Soo KimJeong Ho Cho
    • Nak Cheol SungMin Soo KimJeong Ho Cho
    • H01L4108
    • H03H9/562H03H3/02Y10T29/42Y10T29/43Y10T29/435Y10T29/49121Y10T29/49146Y10T29/49169Y10T29/49171Y10T29/49789Y10T29/49798
    • A high frequency resonator and a manufacturing method therefor are disclosed. The method for manufacturing a ceramic resonator includes the step of forming a ceramic piezoelectric device, a capacitor chip and a lead frame. Then the piezoelectric device and the capacitor chip are assembled into the lead frame, and the assembled chip is molded by using epoxy resin. The process for making the capacitor includes the step of cutting a ceramic wafer into a plurality of sub-wafers. Then electrodes are printed on one face of the sub-wafer in a dual-striped form, and a drying is carried out on the sub-wafer thus printed. Then another electrode is printed on a central part of the opposite face of the sub-wafer in such a manner as to be overlapped with the electrodes of the one face of the sub-wafer. Then the sub-wafer is dried. Then a baking is carried out on the sub-wafer thus dried, and the sub-wafer thus baked is cut into a plurality of capacitor chips.
    • 公开了一种高频谐振器及其制造方法。 制造陶瓷谐振器的方法包括形成陶瓷压电器件,电容器芯片和引线框架的步骤。 然后将压电器件和电容器芯片组装到引线框架中,并且使用环氧树脂模制组装的芯片。 制造电容器的过程包括将陶瓷晶片切割成多个子晶片的步骤。 然后将电极以双重条纹形式印刷在子晶片的一个面上,并且在这样印刷的子晶片上进行干燥。 然后以与子晶片的一个面的电极重叠的方式将另一电极印刷在子晶片的相对面的中心部分上。 然后将该副晶片干燥。 然后在这样干燥的子晶片上进行烘烤,将这样烘烤的子晶片切成多个电容器芯片。
    • 80. 发明授权
    • Latency circuit and semiconductor device comprising same
    • 延迟电路和包括该延迟电路的半导体器件
    • US08437206B2
    • 2013-05-07
    • US12857762
    • 2010-08-17
    • In-Woo JunByung Hoon JeongMin Soo Kim
    • In-Woo JunByung Hoon JeongMin Soo Kim
    • G11C7/00
    • G11C7/22G11C7/222G11C7/227G11C8/18G11C2207/2272
    • A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.
    • 延迟电路包括等待时间控制块,内部读命令发生器和等待时间信号生成单元。 等待时间控制块通过延迟基于外部时钟产生的延迟同步信号来产生多个第一控制时钟,并且生成相对于基于延迟同步信号解码的读命令具有余量的第二控制时钟。 内部读命令生成器使用解码读命令对第二控制时钟进行采样,并根据采样的第二控制时钟生成内部读指令。 等待时间信号生成单元基于使用多个第一控制时钟对内部读取命令执行的移位操作生成等待时间信号。