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71. 发明授权

US06537880B1 Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch isolation and large capacitance between control and floating gates 有权
标题翻译：制造具有窄间隔隔离度的高密度NAND堆叠栅极闪存器件和控制和浮置栅极之间的大电容的方法
公开(公告)号：US06537880B1
公开(公告)日：2003-03-25
申请号：US09950609
申请日：2001-09-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/32139 , H01L29/42324
摘要： A process for fabricating a flash memory cell with increased floating gate to control gate overlap, has been developed. The process features forming the active device region of the flash memory cell in a narrow space of a semiconductor substrate, located between STI regions. The increased overlap is achieved via formation of a floating gate structure comprised with vertical conductive spacers, extending upwards from the periphery of an underlying floating gate base structure. Novel process sequences are used to simultaneously form the vertical conductive spacers and the floating gate base structure.
摘要翻译：已经开发了用于制造具有增加的浮动栅极以控制栅极重叠的闪存单元的工艺。该工艺特征在于在位于STI区域之间的半导体衬底的狭窄空间中形成闪存单元的有源器件区域。增加的重叠通过形成由垂直导电间隔件构成的浮动栅极结构来实现，该浮动栅极结构从下面的浮动栅极基极结构的外围向上延伸。新的工艺顺序用于同时形成垂直导电间隔物和浮动栅极基底结构。

72. 发明授权

US06495420B2 Method of making a single transistor non-volatile memory device 有权
标题翻译：制造单晶体管非易失性存储器件的方法
公开(公告)号：US06495420B2
公开(公告)日：2002-12-17
申请号：US09782238
申请日：2001-02-12
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/42324 , H01L21/28273
摘要： The present invention includes forming a first oxide layer as a sacrificial dielectric layer on a semiconductor substrate. A nitride layer is formed on the sacrificial dielectric layer. Then, the sacrificial dielectric layer and the nitride layer are patterned to form an opening. Next, a second oxide layer is formed on the nitride layer and along a surface of the opening. Side wall spacers are created by etching. Then, a gate dielectric layer is formed on the exposed semiconductor substrate. A first polysilicon layer is deposited on the nitride layer. Subsequently, the first polysilicon layer is polished by CMP, followed by removing the nitride layer, the spacers and the sacrificial dielectric layer. A tunneling dielectric layer and a control gate are respectively formed on a surface of the floating gate.
摘要翻译：本发明包括在半导体衬底上形成作为牺牲电介质层的第一氧化物层。在牺牲电介质层上形成氮化物层。然后，将牺牲介电层和氮化物层图案化以形成开口。接下来，在氮化物层上并且沿着开口的表面形成第二氧化物层。通过蚀刻产生侧壁间隔物。然后，在暴露的半导体衬底上形成栅介质层。第一多晶硅层沉积在氮化物层上。随后，通过CMP抛光第一多晶硅层，然后除去氮化物层，间隔物和牺牲介电层。隧道电介质层和控制栅分别形成在浮动栅极的表面上。

73. 发明授权

US06455428B1 Method of forming a metal silicide layer 有权
标题翻译：形成金属硅化物层的方法
公开(公告)号：US06455428B1
公开(公告)日：2002-09-24
申请号：US09696080
申请日：2000-10-26
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31058 , H01L21/76814
摘要： A process for forming a metal silicide layer on the surface of a conductive region in a semiconductor substrate, located at the bottom of a contact hole formed in an insulator layer, has been developed. The process features the removal of a photoresist shape, used to define the contact hole, via removal procedures that avoid the formation of a substoichiometric, silicon oxide, native oxide layer, on the top surface of the conductive region. The removal of the contact hole defining photoresist shape is realized via a chemical mechanical polishing procedure, which results in no native oxide formation, or removal of the photoresist shape can be accomplished via a combination of chemical mechanical polishing and wet clean procedure, which will form a native oxide layer, however only comprised of easily removable stoichiometric silicon oxide. The inability to remove substoichiometric silicon oxide, formed from procedures such as plasma oxygen ashing, can deleteriously influence the formation of metal silicide layers on the surface of a conductive region.
摘要翻译：已经开发了在位于形成在绝缘体层中的接触孔的底部的半导体衬底的导电区域的表面上形成金属硅化物层的工艺。该方法的特征在于通过去除程序去除用于限定接触孔的光致抗蚀剂形状，该方法避免了在导电区域的顶表面上形成亚化学计量的氧化硅自然氧化物层。通过化学机械抛光程序实现了形成光刻胶形状的接触孔的去除，这导致没有自然氧化物形成，或者可以通过化学机械抛光和湿清洁程序的组合来实现光致抗蚀剂形状的去除，这将形成天然氧化物层，然而仅由易于除去的化学计量的氧化硅组成。不能除去由诸如等离子体氧灰化的过程形成的亚化学计量氧化硅可有害地影响导电区域表面上的金属硅化物层的形成。

74. 发明授权

US06395603B1 Method of forming a tunnel oxide layer of a non-volatile memory cell 有权
标题翻译：形成非易失性存储单元的隧道氧化物层的方法
公开(公告)号：US06395603B1
公开(公告)日：2002-05-28
申请号：US09745334
申请日：2000-12-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L213105
CPC分类号： H01L21/32135 , H01L21/28273 , H01L21/32105 , H01L21/32137 , Y10S438/964
摘要： A method of forming a tunnel oxide layer of a non-volatile memory cell is disclosed. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. After patterning the second dielectric layer to form an opening, the semiconductor substrate is oxidized to form a non-tunnel oxide within the opening. After removing the second dielectric layer, source/drain regions are formed by performing an ion implantation process and an annealing process. After removing the first dielectric layer, an HSG layer with a plurality of HSG grains are formed on the source/drain regions. After that, the HSG layer is partially etched by HF vapor to enlarge a spacing between the HSG grains. Finally, the HSG layer is oxidized to form the tunnel oxide layer.
摘要翻译：公开了一种形成非易失性存储单元的隧道氧化物层的方法。首先，在半导体衬底上形成第一电介质层和第二电介质层。在图案化第二电介质层以形成开口之后，半导体衬底被氧化以在开口内形成非隧道氧化物。在去除第二电介质层之后，通过进行离子注入工艺和退火工艺形成源极/漏极区域。在去除第一电介质层之后，在源/漏区上形成具有多个HSG晶粒的HSG层。之后，HSG层被HF蒸汽部分蚀刻，以扩大HSG晶粒之间的间距。最后，HSG层被氧化形成隧道氧化层。

75. 发明授权

US06391711B1 Method of forming electrical connection between stack capacitor and node location of substrate 有权
标题翻译：堆叠电容器与基板节点位置之间形成电连接的方法
公开(公告)号：US06391711B1
公开(公告)日：2002-05-21
申请号：US09677810
申请日：2000-10-03
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2144
CPC分类号： H01L27/10855 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L27/10811 , H01L27/10888 , H01L28/84 , H01L28/91
摘要： The present invention relates to a method of forming a contact pedestal for an electrical connection between a stack capacitor and a node location of a substrate. The present invention is characterized by forming, just based on patterning a mask layer twice, a hole in the shape of a stud in the dielectric material deposited over the node location, to make a contact pedestal in the shape of a stud for an electrical connection between a node location of a FET in a substrate, and a stack capacitor spaced from the substrate by the dielectric material.
摘要翻译：本发明涉及形成用于堆叠电容器和衬底的节点位置之间的电连接的接触基座的方法。本发明的特征在于，基于将掩模层图案化两次，形成沉积在节点位置上的电介质材料中的螺柱形状的孔，以形成用于电连接的螺柱形状的接触基座在衬底中的FET的节点位置和通过电介质材料与衬底间隔开的堆叠电容器之间。

76. 发明授权

US06358800B1 Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit 有权
标题翻译：形成具有沟槽长度超过光刻极限的凹入栅极的MOSFET的方法
公开(公告)号：US06358800B1
公开(公告)日：2002-03-19
申请号：US09664477
申请日：2000-09-18
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L21/3086 , H01L21/3088 , H01L29/66621 , H01L29/7834
摘要： A method of forming a MOSFET having a recessed-gate with a channel length beyond the photolithography limit is disclosed in the present invention. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. A first opening is next formed in the second dielectric layer. After forming first spacers on sidewalls of the first opening and removing the first dielectric layer within the first opening, a trench is formed in the semiconductor substrate by an anisotropic etching process. After forming second spacers with dopant source material on sidewalls of the trench, a gate dielectric layer is formed within the trench. A conductive layer is formed to refill said trench. After removing the portion of the conductive layer outside the trench, a gate plug is then formed. After removing the second dielectric layer, source and drain regions and source/drain extensions are formed
摘要翻译：在本发明中公开了一种形成具有超过光刻极限的沟道长度的凹入栅极的MOSFET的方法。首先，在半导体衬底上形成第一电介质层和第二电介质层。接下来在第二电介质层中形成第一开口。在第一开口的侧壁上形成第一间隔物并且去除第一开口内的第一电介质层之后，通过各向异性蚀刻工艺在半导体衬底中形成沟槽。在沟槽的侧壁上形成具有掺杂剂源材料的第二间隔物之后，在沟槽内形成栅极电介质层。形成导电层以再填充所述沟槽。在沟槽外部去除导电层的部分之后，形成栅极插头。在去除第二电介质层之后，形成源极和漏极区域以及源极/漏极延伸部分

77. 发明授权

US06294413B1 Method for fabricating a SOI (silicon on insulator) device 有权
标题翻译： SOI（绝缘体上硅）器件的制造方法
公开(公告)号：US06294413B1
公开(公告)日：2001-09-25
申请号：US09751917
申请日：2000-12-27
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2184
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method for fabricating an SOI semiconductor device with reduced floating body effects and a simplified method of fabrication. In the invention, a N-type doped dielectric layer or P-type doped dielectric layer is used to be driven into the semiconductor layer to form source/drain regions of field effect transistors of CMOS and conductive regions. For fabricating a NMOS transistor and a PMOS transistor of the CMOS device, the invention provides a method which an ion implantation process and a photo mask are omitted, by which the method will decrease the complexity of the fabrication process and the cost thereof.
摘要翻译：一种用于制造具有减小的浮体效应的SOI半导体器件的方法和简化的制造方法。在本发明中，使用N型掺杂介质层或P型掺杂介电层驱动到半导体层中，形成CMOS和导电区域的场效应晶体管的源极/漏极区域。为了制造CMOS器件的NMOS晶体管和PMOS晶体管，本发明提供了一种离子注入工艺和光掩模被省略的方法，通过该方法将降低制造工艺的复杂性及其成本。

78. 发明授权

US06277688B1 Method of manufacturing a DRAM capacitor with increased electrode surface area 有权
标题翻译：制造具有增加的电极表面积的DRAM电容器的方法
公开(公告)号：US06277688B1
公开(公告)日：2001-08-21
申请号：US09609267
申请日：2000-06-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： A method of manufacturing a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a capacitor opening through a dielectric isolation interlayer to expose a buried contact area. A conductive bottom plug is subsequently formed in a bottom portion of the capacitor opening and makes an electrical connection with the contact area. A conductive spacer is formed on the sidewall of the opening and then a dielectric spacer is formed on the sidewall of the conductive spacer. Such leaves a channel in the center of the capacitor opening. A conductive center column is therefore in the channel. Subsequently, the dielectric spacer is removed while leaving the conductive sidewall spacer, center column, and bottom plug to serve as a bottom storage node of the capacitor. Finally, a capacitor dielectric layer and a top storage node are formed to complete the capacitor fabrication.
摘要翻译：公开了制造动态随机存取存储器单元的电容器的方法。该方法包括通过介电隔离中间层形成电容器开口以暴露埋入的接触区域。导电底塞随后形成在电容器开口的底部，并与接触区域电连接。导电间隔物形成在开口的侧壁上，然后在导电间隔物的侧壁上形成介电隔离物。这样在电容器开口的中心留下通道。因此，导电中心列在通道中。随后，去除电介质间隔物，同时留下导电侧壁间隔物，中心柱和底部塞以用作电容器的底部存储节点。最后，形成电容器介质层和顶部存储节点以完成电容器制造。

79. 发明授权

US06271072B1 Method of manufacturing a storage node having five polysilicon bars 有权
标题翻译：制造具有五个多晶硅棒的存储节点的方法
公开(公告)号：US06271072B1
公开(公告)日：2001-08-07
申请号：US09332424
申请日：1999-06-14
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218234
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/92
摘要： A method for forming a dynamic random access memory cell with an increased capacitance capacitor having a storage node with five polysilicon bars is achieved. A photoresist mask is formed overlying a portion of a first polysilicon layer filling an opening through a dielectric layer to a node contact region. The photoresist mask is silylated to form a top silylated photoresist portion and silylated photoresist sidewalls on the surfaces of the photoresist mask. The top silylated photoresist portion and the unsilylated mask are removed. A portion of the first polysilicon layer is etched away where it is not covered by the silylated photoresist sidewalls thereby forming two first polysilicon bars underlying the silylated photoresist sidewalls and leaving a second thickness of the first polysilicon layer smaller than its first thickness. The silylated photoresist sidewalls are removed. A second dielectric layer is deposited over the first polysilicon layer and is anisotropically etched back to form spacers on either side of the two polysilicon bars. A second polysilicon layer is deposited and the first and second polysilicon layers are anisotropically etched back to form three second polysilicon bars and a T-shaped first polysilicon layer. The dielectric spacers are removed whereby the T-shaped first polysilicon layer and the two first polysilicon bars and three second polysilicon bars make five polysilicon bars which together form a storage node of the capacitor.
摘要翻译：实现了具有增加的电容电容器的动态随机存取存储单元的形成方法，其具有具有五个多晶硅条的存储节点。在第一多晶硅层的一部分上形成光致抗蚀剂掩模，第一多晶硅层填充通过电介质层的开口到节点接触区域。光致抗蚀剂掩模被甲硅烷基化以在光致抗蚀剂掩模的表面上形成顶部甲硅烷基化的光致抗蚀剂部分和甲硅烷基化的光致抗蚀剂侧壁。去除顶部甲硅烷基化的光致抗蚀剂部分和非乙化的掩模。第一多晶硅层的一部分被蚀刻掉，其中它不被甲硅烷基化的光致抗蚀剂侧壁覆盖，从而在甲硅烷基化的光致抗蚀剂侧壁下面形成两个第一多晶硅条，并留下第一多晶硅层的第二厚度小于其第一厚度。去除甲硅烷基化的光致抗蚀剂侧壁。第二介电层沉积在第一多晶硅层上，并被各向异性地回蚀以在两个多晶硅条的两侧形成间隔物。沉积第二多晶硅层，并将第一和第二多晶硅层各向异性地回蚀以形成三个第二多晶硅条和T形第一多晶硅层。去除电介质间隔物，由此T形第一多晶硅层和两个第一多晶硅条和三个第二多晶硅条形成五个多晶硅条，它们一起形成电容器的存储节点。

80. 发明授权

US06261901B1 Method of manufacturing a DRAM capacitor with a dielectric column 有权
标题翻译：制造具有电介质柱的DRAM电容器的方法
公开(公告)号：US06261901B1
公开(公告)日：2001-07-17
申请号：US09609266
申请日：2000-06-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L27/10852 , H01L28/84 , H01L28/91
摘要： A method of manufacturing a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a capacitor opening through a dielectric isolation interlayer to expose a buried contact area. A plug of conductive material is subsequently formed in a bottom portion of the capacitor opening and makes an electrical connection with the contact area. A conductive spacer is formed on the sidewall of the opening by depositing a conformal layer and anisotropically etching back, and such leaves a channel within the opening. A dielectric column is formed by filling the channel with dielectric material. The lateral surface of the dielectric column is then exposed by removing the laterally adjacent conductive spacer. Finally, first and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the dielectric column, thereby completing the capacitor.
摘要翻译：公开了制造动态随机存取存储器单元的电容器的方法。该方法包括通过介电隔离中间层形成电容器开口以暴露埋入的接触区域。随后在电容器开口的底部形成导电材料塞，并与接触区域电连接。通过沉积保形层并各向异性地回蚀而形成在开口的侧壁上的导电间隔物，并且这样在该开口内留下通道。通过用电介质材料填充沟道形成电介质柱。然后通过去除横向相邻的导电间隔物来暴露电介质柱的侧表面。最后，第一和第二电容器板及其之间的电介质层形成在电容器开口内并被电介质柱支撑，从而完成电容器。

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