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71. 发明授权

US08750037B2 Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof 有权
标题翻译：利用冲击电离和隧穿的非易失性存储器及其制造方法
公开(公告)号：US08750037B2
公开(公告)日：2014-06-10
申请号：US12456440
申请日：2009-06-16
申请人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
发明人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
IPC分类号： G11C16/04
CPC分类号： H01L29/7885 , G11C16/0408 , H01L29/42336 , H01L29/66825
摘要： A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
摘要翻译：公开并构造了非易失性存储器件（和制造方法），以使得能够在器件的第一部分中使用电离冲击处理的写入操作以及在器件的第二部分中使用隧道工艺的读取操作。非易失性存储器件（1）增加了热载流子注入效率，（2）降低功耗，（3）使非易失性存储器件中的电压和器件缩放。

72. 发明授权

US08698118B2 Compact RRAM device and methods of making same 有权
标题翻译：紧凑的RRAM设备及其制作方法
公开(公告)号：US08698118B2
公开(公告)日：2014-04-15
申请号：US13408221
申请日：2012-02-29
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04 , H01L29/06
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
摘要翻译：这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间的至少一个可变电阻材料层。

73. 发明授权

US08674332B2 RRAM device with an embedded selector structure and methods of making same 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制作方法
公开(公告)号：US08674332B2
公开(公告)日：2014-03-18
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

74. 发明授权

US08633081B2 Modifying growth rate of a device layer 有权
标题翻译：修改设备层的增长速度
公开(公告)号：US08633081B2
公开(公告)日：2014-01-21
申请号：US12980376
申请日：2010-12-29
申请人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
发明人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/2822 , H01L21/76232
摘要： A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.
摘要翻译：一种器件包括具有其上形成有晶体管的器件区域的衬底。器件区域包括有效边缘区域和具有不同氧化生长速率的活性中心区域。使用包含修饰氧化生长速率的掺杂剂的生长速率调节剂（GRM）来制造具有均匀厚度的栅极氧化物层。取决于所使用的掺杂剂的类型，GRM可以增强或延缓氧化生长。氟掺杂剂增强氧化生长速率，而氮掺杂剂延缓氧化生长速率。

75. 发明申请

US20140008713A1 METHOD AND APPARATUS FOR EMBEDDED NVM UTILIZING AN RMG PROCESS 有权
标题翻译：用于嵌入式NVM的方法和装置利用RMG过程
公开(公告)号：US20140008713A1
公开(公告)日：2014-01-09
申请号：US13543340
申请日：2012-07-06
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L21/8239 , H01L27/088
CPC分类号： H01L21/823437 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L27/11524 , H01L29/66545
摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
摘要翻译：通过集成嵌入式非易失性存储器（eNVM）与RMG进程来制造存储器件。实施例包括在衬底的上表面上形成第一和第二双多晶硅栅叠层结构，在第一和第二双多晶硅栅叠层结构中的每一个的相对侧壁上形成间隔物，形成与露出侧壁相邻的ILD 移除所述第一双多晶硅栅堆叠结构，在所述间隔物之间形成第一空腔，并在所述第一空腔中形成HKMG，其中所述HKMG形成存取栅极。

76. 发明申请

US20130270501A1 RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME 有权
标题翻译：具有嵌入式选择器结构的RRAM器件及其制造方法
公开(公告)号：US20130270501A1
公开(公告)日：2013-10-17
申请号：US13445658
申请日：2012-04-12
申请人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/04 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
摘要翻译：本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间的导电字线电极和第一和第二区域分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

77. 发明申请

US20130240821A1 THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME 有权
标题翻译：三维RRAM装置及其制造方法
公开(公告)号：US20130240821A1
公开(公告)日：2013-09-19
申请号：US13423793
申请日：2012-03-19
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2409 , H01L27/2445 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.
摘要翻译：本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极线和第二位线的可变电阻材料。

78. 发明授权

US08470700B2 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
公开(公告)号：US08470700B2
公开(公告)日：2013-06-25
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L21/26
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

79. 发明授权

US08368127B2 Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current 有权
标题翻译：制造具有高驱动电流的硅隧道场效应晶体管（TFET）的方法
公开(公告)号：US08368127B2
公开(公告)日：2013-02-05
申请号：US12587511
申请日：2009-10-08
申请人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , B82Y10/00 , H01L29/0895 , H01L29/7391 , H01L29/7606 , H01L29/7613
摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
摘要翻译：制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

80. 发明授权

US08324031B2 Diffusion barrier and method of formation thereof 有权
标题翻译：扩散屏障及其形成方法
公开(公告)号：US08324031B2
公开(公告)日：2012-12-04
申请号：US12144652
申请日：2008-06-24
申请人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
发明人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
IPC分类号： H01L21/00
CPC分类号： H01L29/66537 , H01L21/26506 , H01L21/266 , H01L21/3223 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L23/532 , H01L27/088 , H01L29/0649 , H01L29/1083 , H01L29/32 , H01L29/36 , H01L29/66477 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
摘要翻译：提出了一种形成装置的方法。该方法包括提供具有第一和第二区域的结构。在第一和第二区域的至少一部分之间形成扩散阻挡层。扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

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