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71. 发明申请

US20080091848A1 Multi-input/output serial peripheral interface and method for data transmission 有权
标题翻译：多输入/输出串行外设接口和数据传输方法
公开(公告)号：US20080091848A1
公开(公告)日：2008-04-17
申请号：US11896846
申请日：2007-09-06
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F3/00
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.
摘要翻译：集成电路的多输入/输出串行外围接口包括耦合到集成电路的许多引脚。集成电路在仅选择性地仅使用多输入/输出串行外围接口的第一引脚，第二引脚，第三引脚和第四引脚的第一引脚或其组合的控制下接收指令。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚接收地址。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚发送读出数据。

72. 发明授权

US07345917B2 Non-volatile memory package and method of reading stored data from a non-volatile memory array 有权
标题翻译：非易失性存储器包和从非易失性存储器阵列读取存储的数据的方法
公开(公告)号：US07345917B2
公开(公告)日：2008-03-18
申请号：US11293239
申请日：2005-12-05
申请人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
发明人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/26
摘要： A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.
摘要翻译：非易失性存储器封装包括具有串联电耦合的多个晶体管的非易失性存储器阵列，每个晶体管具有输入端和输出端，使得晶体管中的一个的输出端耦合到下游晶体管的输入端子沿下游方向。读取电压电源向多个晶体管中所选择的晶体管的输入端提供电压，以在所选择的晶体管的输入端和输出端之间感应出电池电流。位传感器从所选择的晶体管的输出端接收并评估读取电流。屏蔽电压施加器对多个晶体管的下游晶体管的输入端子或输出端子施加电压，下游晶体管处于从所选晶体管的下游方向。

73. 发明申请

US20070127293A1 Non-volatile memory package and method of reading stored data from a non-volatile memory array 有权
标题翻译：非易失性存储器包和从非易失性存储器阵列读取存储的数据的方法
公开(公告)号：US20070127293A1
公开(公告)日：2007-06-07
申请号：US11293239
申请日：2005-12-05
申请人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
发明人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/26
摘要： A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.
摘要翻译：非易失性存储器封装包括具有串联电耦合的多个晶体管的非易失性存储器阵列，每个晶体管具有输入端和输出端，使得晶体管中的一个的输出端耦合到下游晶体管的输入端子沿下游方向。读取电压电源向多个晶体管中所选择的晶体管的输入端提供电压，以在所选择的晶体管的输入端和输出端之间感应出电池电流。位传感器从所选择的晶体管的输出端接收并评估读取电流。屏蔽电压施加器对多个晶体管的下游晶体管的输入端子或输出端子施加电压，下游晶体管处于从所选晶体管的下游方向。

74. 发明申请

US20060233034A1 Circuit and Method for High Speed Sensing 有权
标题翻译：高速检测电路及方法
公开(公告)号：US20060233034A1
公开(公告)日：2006-10-19
申请号：US11421905
申请日：2006-06-02
申请人： Chun-Hsiung Hung , Su-Chueh Lo , Shou Huang
发明人： Chun-Hsiung Hung , Su-Chueh Lo , Shou Huang
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/14 , G11C11/4091 , G11C11/4099
摘要： A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to the first and second signals, determining the time at which the second voltage developed in response to the second signal reaches a threshold level above a latch switching point, and latching a state of the first voltage and second voltage at the determined time using a latch circuit. The threshold level above the latch switching point is set so that potential mismatch in the components of the latch circuit is overcome prior to latching.
摘要翻译：用于感测诸如来自存储器单元的源侧的信号的第一信号与来自参考虚拟单元的信号的第二信号之间的差异的电路和方法包括分别响应地开发第一和第二电压对于第一和第二信号，确定响应于第二信号而产生的第二电压的时间达到高于锁存开关点的阈值电平，并且使用锁存器在所确定的时间锁存第一电压和第二电压的状态电路。锁存开关点之上的阈值电平被设定为使得在锁存之前克服锁存电路的部件中的电位失配。

75. 发明申请

US20060092709A1 Devices and methods to improve erase uniformity and to screen for marginal cells for NROM memories 有权
公开(公告)号：US20060092709A1
公开(公告)日：2006-05-04
申请号：US11096878
申请日：2005-04-01
申请人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
发明人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/04 , G11C16/3445 , G11C29/50 , G11C29/50004 , G11C29/52
摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

76. 发明授权

US06795350B2 Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line 有权
标题翻译：用于通过可选地切割电容性参考位线来将参考位线负载调谐到读出放大器的电路和方法
公开(公告)号：US06795350B2
公开(公告)日：2004-09-21
申请号：US10351528
申请日：2003-01-27
申请人： Han-Sung Chen , Kuo-Yu Liao , Chen-Hao Po , Chun-Hsiung Hung
发明人： Han-Sung Chen , Kuo-Yu Liao , Chen-Hao Po , Chun-Hsiung Hung
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C7/062 , G11C7/12 , G11C16/28 , G11C29/02 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2207/2254
摘要： A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.
摘要翻译：用于将参考位线加载到读出放大器的电路和方法，所述读出放大器将感测节点上的电压与参考数据线节点上的电压进行比较，以确定读出放大器的输出上的感测信号。感测节点被选择性地连接到存储器单元以在感测节点上产生感测的电压，以表示存储在所选择的存储器单元中的数据。包括连接到参考数据线节点的参考单元单元和参考位线单元。参考单元单元包含至少一个参考单元，以向参考位线节点提供参考电流，并且参考位线单元包含可选地切割的至少一个参考位线，以确定参考位线负载。

77. 发明授权

US06366519B1 Regulated reference voltage circuit for flash memory device and other integrated circuit applications 失效
标题翻译：用于闪存器件和其他集成电路应用的稳压参考电压电路
公开(公告)号：US06366519B1
公开(公告)日：2002-04-02
申请号：US08624389
申请日：1996-04-05
申请人： Chun-Hsiung Hung , Tien-Ler Lin , Kota Soejima , Satoshi Matsubara
发明人： Chun-Hsiung Hung , Tien-Ler Lin , Kota Soejima , Satoshi Matsubara
IPC分类号： G11C1300
CPC分类号： G11C16/30 , G11C5/145 , G11C5/147
摘要： A charge pump circuit which generates an output voltage at a selected level, but variations in the current supplied to the charge pump are limited, and variations in the output current generated by the charge pump are limited. The charge pump circuit is coupled to a power supply which has a supply voltage which varies over a specified range. It includes a first charge pump that generates a reference voltage higher than the supply voltage in response to the supply voltage. A circuit, coupled to the first charge pump and responsive to the reference voltage generates a regulated supply voltage. A second charge pump generates a controlled output voltage in response to the regulated supply voltage. The regulated supply voltage is used by pump clock drivers and as a pump reference supply for the second charge pump.
摘要翻译：产生选定电平的输出电压但供给电荷泵的电流的变化的电荷泵电路受到限制，电荷泵产生的输出电流的变化受到限制。电荷泵电路耦合到具有在指定范围内变化的电源电压的电源。它包括第一电荷泵，其产生响应于电源电压而高于电源电压的参考电压。耦合到第一电荷泵并响应于参考电压的电路产生稳定的电源电压。第二电荷泵响应于稳定的电源电压产生受控的输出电压。调节电源电压由泵浦时钟驱动器和第二个电荷泵的泵参考电源使用。

78. 发明授权

US5955893A Power saving buffer circuit buffer bias voltages 失效
标题翻译：省电缓冲电路缓冲偏置电压
公开(公告)号：US5955893A
公开(公告)日：1999-09-21
申请号：US767447
申请日：1996-12-16
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Yin-Shang Liu
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Yin-Shang Liu
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/0013 , H03K19/018521
摘要： An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage. The level shifter provides a relatively constant second bias voltage by providing a relatively constant voltage shift V.sub.LS between a level shifter reference voltage V.sub.ref and the bias node. In the present embodiment, this voltage shift V.sub.LS is the absolute value of the gate to source threshold voltage of a FET. Accordingly, the second bias voltage is V.sub.ref -V.sub.LS. In one embodiment, the voltage control circuit includes a second level shifter to provide the first bias voltage.
摘要翻译：本发明的实施例提供了具有降低的功耗的缓冲电路。缓冲电路包括耦合到偏置节点处的缓冲器的省电开关。例如，缓冲器具有适于以TTL电平接收输入电压的输入，并且具有适于在CMOS电平处提供输出电压的输出。省电开关包括电平转换器和两个耦合到偏置节点的电压控制电路。缓冲器的输出电压反馈给省电开关。当输出电压处于低CMOS电平时，省电开关使用电压控制电路向偏置节点提供第一偏置电压。当输出电压处于高CMOS电平时，省电开关使用电平移位器向偏置节点提供第二偏置电压。第二偏置电压被选择为使得其在预定的输入截止电压下防止偏置节点和缓冲器之间的电流流动。电平移位器通过在电平移位器参考电压Vref和偏置节点之间提供相对恒定的电压偏移VLS来提供相对恒定的第二偏置电压。在本实施例中，该电压偏移VLS是FET的栅极 - 源极阈值电压的绝对值。因此，第二偏置电压为Vref-VLS。在一个实施例中，电压控制电路包括提供第一偏置电压的第二电平移位器。

79. 发明授权

US09093130B2 Sense amplifier with shielding circuit 有权
标题翻译：带屏蔽电路的感应放大器
公开(公告)号：US09093130B2
公开(公告)日：2015-07-28
申请号：US13474270
申请日：2012-05-17
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/02 , G11C7/06
CPC分类号： G11C7/062 , G11C7/02
摘要： A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit.
摘要翻译：读出放大器包括第一晶体管，第二晶体管，输出电路和屏蔽电路。第一晶体管具有由单元电流建立的栅极偏置，并且第二晶体管具有由参考电流建立的栅极偏置。输出电路耦合到第一和第二晶体管。屏蔽电路位于第二晶体管和输出电路之间。

80. 发明授权

US09036410B2 Y-decoder and decoding method thereof 有权
标题翻译： Y解码器及其解码方法
公开(公告)号：US09036410B2
公开(公告)日：2015-05-19
申请号：US13013592
申请日：2011-01-25
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C16/06 , G11C8/10
CPC分类号： G11C8/10
摘要： A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.
摘要翻译： Y解码器包括选择单元和Y-MUX。选择单元耦合到用于选择列线的存储器阵列。 Y-MUX耦合到选择单元，用于向所选择的列线提供电压。 Y-MUX包括并联耦合的第一开关，第二开关，第三开关和第四开关。第一开关和第二开关分别用于接收第一屏蔽电压和第二屏蔽电压。第三开关和第四开关分别用于接收第一感测电压和第二感测电压。

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