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71. 发明授权

US09241426B2 Air-based geothermal cooling system for a telecom utility cabinet 有权
标题翻译：用于电信实用柜的空气地热冷却系统
公开(公告)号：US09241426B2
公开(公告)日：2016-01-19
申请号：US13184948
申请日：2011-07-18
申请人： Pedro Fernandez , Shanjiu Chi , Amit Kulkarni , Liqian Zhai , Kelly C. Johnson , Yong Lu , Mahmoud Elkenaney
发明人： Pedro Fernandez , Shanjiu Chi , Amit Kulkarni , Liqian Zhai , Kelly C. Johnson , Yong Lu , Mahmoud Elkenaney
IPC分类号： F28D1/02 , F28F27/02 , F28F9/26 , H05K7/20 , F24J3/08
CPC分类号： H05K7/2059 , F24T10/10 , Y02E10/12
摘要： In one embodiment, the disclosure includes an air-based geothermal cooling system for a telecom utility cabinet. The air-based geothermal cooling system includes a plurality of heat exchange tubes configured to extend into an underground environment. The air-based geothermal cooling system also includes an input/output (I/O) manifold coupled to the plurality of heat exchange tubes and providing an airway between the plurality of heat exchange tubes and the telecom utility cabinet.
摘要翻译：在一个实施例中，本公开包括用于电信公用柜的基于空气的地热冷却系统。基于空气的地热冷却系统包括构造成延伸到地下环境中的多个热交换管。基于空气的地热冷却系统还包括联接到多个热交换管的输入/输出（I / O）歧管，并且在多个热交换管和电信实用柜之间提供气道。

72. 发明授权

US09030867B2 Bipolar CMOS select device for resistive sense memory 有权
标题翻译：用于电阻读出存储器的双极CMOS选择器件
公开(公告)号：US09030867B2
公开(公告)日：2015-05-12
申请号：US12502211
申请日：2009-07-13
申请人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
发明人： Yong Lu , Hongyue Liu , Maroun Khoury , Yiran Chen
IPC分类号： G11C11/00 , G11C11/34 , G11C13/00 , G11C11/16
CPC分类号： G11C13/0004 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2213/76
摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
摘要翻译：电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。每个晶体管包括发射极触点和集电极触点。每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

73. 发明授权

US08942556B2 Optical transceiver integrated with optical time domain reflectometer monitoring 有权
标题翻译：光收发器集成了光时域反射仪监控
公开(公告)号：US08942556B2
公开(公告)日：2015-01-27
申请号：US13309983
申请日：2011-12-02
申请人： Fuqiang Zhao , Yi Yang , Yong Lu
发明人： Fuqiang Zhao , Yi Yang , Yong Lu
IPC分类号： H04B10/08 , H04B10/272 , H04B10/071 , H04B10/40 , H04B10/00
CPC分类号： H04B10/272 , H04B10/071 , H04B10/40
摘要： An optical transceiver having an integrated optical time domain reflectometer monitoring unit and methods for using the same are disclosed. The disclosure relates to an optical transceiver comprising an optical device comprising a wavelength division multiplexing system (WDM), a data signal driver, a data signal limiting amplifier, and an optical time domain reflectometer (OTDR) data processing module. Furthermore, the optical transceiver is particularly advantageous in an optical line terminal (OLT) and/or a passive optical network (PON). The integrated OTDR data processing module can protect the optical transceiver, ensure successful monitoring data, simplify network wiring and decrease system and network costs by decreasing the number of OTDR modules and WDM units.
摘要翻译：公开了一种具有集成光时域反射计监视单元的光收发器及其使用方法。本公开涉及一种光收发器，包括包括波分复用系统（WDM），数据信号驱动器，数据信号限幅放大器和光时域反射计（OTDR）数据处理模块的光学装置。此外，光收发器在光线路终端（OLT）和/或无源光网络（PON）中是特别有利的。集成的OTDR数据处理模块可以通过减少OTDR模块和WDM单元的数量来保护光收发器，确保成功监控数据，简化网络布线，降低系统和网络成本。

74. 发明授权

US08925621B2 Air-based geothermal cooling maintenance system 有权
标题翻译：空基地热冷却维护系统
公开(公告)号：US08925621B2
公开(公告)日：2015-01-06
申请号：US13184960
申请日：2011-07-18
申请人： Pedro Fernandez , Shanjiu Chi , Amit Kulkarni , Liqian Zhai , Kelly C. Johnson , Yong Lu , Mahmoud Elkenaney
发明人： Pedro Fernandez , Shanjiu Chi , Amit Kulkarni , Liqian Zhai , Kelly C. Johnson , Yong Lu , Mahmoud Elkenaney
IPC分类号： F24J3/08 , B60H1/00 , F28D15/00 , F25D23/12 , H05K7/20
CPC分类号： H05K7/2059 , F24T10/10 , Y02E10/12
摘要： In one embodiment, a system includes a telecom utility cabinet and an air-based geothermal cooling system for the telecom utility cabinet. The system also includes a leak detector for the air-based geothermal cooling system. In another embodiment, a method includes detecting a leak in an air-based geothermal cooling system. The method also includes activating a liquid pump for the air-based geothermal cooling system in response to the leak detection.
摘要翻译：在一个实施例中，系统包括电信公用柜和用于电信公用柜的基于空气的地热冷却系统。该系统还包括用于空气基础地热冷却系统的检漏仪。在另一个实施例中，一种方法包括检测基于空气的地热冷却系统中的泄漏。该方法还包括响应于泄漏检测激活用于空气基础地热冷却系统的液体泵。

75. 发明授权

US08520432B2 Magnetic memory with separate read and write paths 失效
标题翻译：具有独立读写路径的磁记忆体
公开(公告)号：US08520432B2
公开(公告)日：2013-08-27
申请号：US12974699
申请日：2010-12-21
申请人： Yong Lu , Hongyue Liu , Zheng Gao , Insik Jin , Dimitar V. Dimitrov
发明人： Yong Lu , Hongyue Liu , Zheng Gao , Insik Jin , Dimitar V. Dimitrov
IPC分类号： G11C11/14
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L43/08
摘要： Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.
摘要翻译：公开了具有分离的读和写路径的磁存储器。磁存储器单元包括具有第一磁化取向的第一端部，具有第二磁化取向的相对的第二端部和第一端部与第二端部之间的中间部分的铁磁条，所述中间部分具有自由磁化方向。第一磁化取向与第二磁化取向相反。隧道势垒将磁性参考层与形成磁性隧道结的中间部分分开。位线电耦合到第二端部。源极线电耦合到第一端部，并且读取线电耦合到磁性隧道结。

76. 发明授权

US08514605B2 MRAM diode array and access method 有权
标题翻译： MRAM二极管阵列和访问方式
公开(公告)号：US08514605B2
公开(公告)日：2013-08-20
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C5/08 , G11C27/00 , G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

77. 发明授权

US08422271B2 Bidirectional non-volatile memory array architecture 有权
标题翻译：双向非易失性存储器阵列架构
公开(公告)号：US08422271B2
公开(公告)日：2013-04-16
申请号：US13400519
申请日：2012-02-20
申请人： Andrew John Carter , Yong Lu
发明人： Andrew John Carter , Yong Lu
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/1659 , G11C11/1675
摘要： Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate structure of each of the switching devices. A plurality of conductive bit lines extend in a second direction adjacent the memory cells, each bit line providing a connection node that interconnects a respective pair of the memory cells. A control circuit senses a programmed state of a selected memory cell by setting each of the bit lines on a first side of the selected memory cell to a first voltage level, setting each of the remaining bit lines on an opposing second side of the selected memory cell to a second voltage level, and setting the word line to a third voltage level.
摘要翻译：用于在存储器中传送数据的方法和装置。半导体存储器包括多个存储单元，每个存储单元具有与开关器件串联的电阻感测元件（RSE）。导电字线在与存储器单元相邻的第一方向上延伸并且连接到每个开关器件的栅极结构。多个导电位线在与存储单元相邻的第二方向上延伸，每个位线提供连接相应的一对存储单元的连接节点。控制电路通过将所选择的存储器单元的第一侧上的每个位线设置为第一电压电平来感测所选择的存储器单元的编程状态，将所选择的存储器的相对的第二侧上的每个剩余位线设置单元到第二电压电平，并将字线设置为第三电压电平。

78. 发明授权

US08402352B2 Multi-bit error correction method and apparatus based on a BCH code and memory system 失效
公开(公告)号：US08402352B2
公开(公告)日：2013-03-19
申请号：US12704231
申请日：2010-02-11
申请人： Yufei Li , Yong Lu , Ying Wang , Hao Yang
发明人： Yufei Li , Yong Lu , Ying Wang , Hao Yang
IPC分类号： H03M13/00
CPC分类号： H03M13/1575 , G06F11/10 , G11C2029/0411 , H03M13/152 , H03M13/1525 , H03M13/1565 , H03M13/17 , H03M13/3746
摘要： Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

79. 发明授权

US08320169B2 Asymmetric write current compensation 有权
标题翻译：不对称写入电流补偿
公开(公告)号：US08320169B2
公开(公告)日：2012-11-27
申请号：US13333598
申请日：2011-12-21
申请人： Wenzhong Zhu , Yong Lu , Xiaobin Wang , Yiran Chen , Alan Xuguang Wang , Xiaohua Lou , Haiwen Xi
发明人： Wenzhong Zhu , Yong Lu , Xiaobin Wang , Yiran Chen , Alan Xuguang Wang , Xiaohua Lou , Haiwen Xi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.
摘要翻译：一种用于补偿非易失性单元中不对称写入电流的装置和方法。单位单元包括开关装置和非对称电阻感测元件（RSE），诸如非对称电阻随机存取存储器（RRAM）元件或非对称自旋转矩传递随机存取存储器（STRAM）元件。 RSE相对于开关装置在物理上定位在单位单元内，使得用于编程RSE的硬方向与单元单元的简单编程方向对齐，并且用于编程RSE的简单方向与硬方向对齐编程单元格

80. 发明授权

US08296620B2 Data devices including multiple error correction codes and methods of utilizing 有权
标题翻译：数据设备包括多个纠错码和利用方法
公开(公告)号：US08296620B2
公开(公告)日：2012-10-23
申请号：US12198516
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
摘要翻译：一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

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