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71. 发明授权

US08028129B2 Dynamically re-classifying data in a shared cache 有权
标题翻译：在共享缓存中动态重新分类数据
公开(公告)号：US08028129B2
公开(公告)日：2011-09-27
申请号：US12497115
申请日：2009-07-02
申请人： Christopher J. Hughes , Yen-Kuang Chen
发明人： Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定数据状态是否指示第一类数据的方法，基于该确定将数据从第二类重新分类为第一类，并将数据移动到基于重新分类，与第一请求者单元相关联的共享缓存的第一部分。描述和要求保护其他实施例。

72. 发明申请

US20110145184A1 METHODS AND SYSTEMS TO TRAVERSE GRAPH-BASED NETWORKS 有权
标题翻译：基于图表的网络的方法和系统
公开(公告)号：US20110145184A1
公开(公告)日：2011-06-16
申请号：US12637228
申请日：2009-12-14
申请人： Kisun You , Christopher J. Hughes , Yen-Kuang Chen
发明人： Kisun You , Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06N5/04 , G06N5/02
CPC分类号： G10L15/063 , G10L15/02 , G10L15/083 , G10L15/19 , G10L15/34
摘要： Methods and systems to translate input labels of arcs of a network, corresponding to a sequence of states of the network, to a list of output grammar elements of the arcs, corresponding to a sequence of grammar elements. The network may include a plurality of speech recognition models combined with a weighted finite state machine transducer (WFST). Traversal may include active arc traversal, and may include active arc propagation. Arcs may be processed in parallel, including arcs originating from multiple source states and directed to a common destination state. Self-loops associated with states may be modeled within outgoing arcs of the states, which may reduce synchronization operations. Tasks may be ordered with respect to cache-data locality to associate tasks with processing threads based at least in part on whether another task associated with a corresponding data object was previously assigned to the thread.
摘要翻译：将对应于网络状态序列的网络的弧的输入标签转换成对应于语法元素序列的弧的输出语法元素的列表的方法和系统。网络可以包括与加权的有限状态机换能器（WFST）组合的多个语音识别模型。遍历可能包括有效的电弧遍历，并且可能包括有效的电弧传播。弧可以并行处理，包括源自多个源状态并被引导到公共目的地状态的弧。与状态相关联的自环可以在状态的输出弧内被建模，这可以减少同步操作。至少部分地基于是否将与对应的数据对象相关联的另一个任务先前分配给线程，可以针对高速缓存数据位置命令任务来将任务与处理线程相关联。

73. 发明申请

US20110138128A1 Technique for tracking shared data in a multi-core processor or multi-processor system 有权
标题翻译：用于跟踪多核处理器或多处理器系统中的共享数据的技术
公开(公告)号：US20110138128A1
公开(公告)日：2011-06-09
申请号：US12592998
申请日：2009-12-07
申请人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
发明人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information among multiple cores in a multi-core processor or multiple processors in a multi-processor system.
摘要翻译：一种在多核处理器或多处理器系统中跟踪共享信息的技术。在一个实施例中，核心识别信息（“核心ID”）用于在多处理器系统中的多核处理器或多个处理器中的多个核之间跟踪共享信息。

74. 发明申请

US20110078340A1 VIRTUAL ROW BUFFERS FOR USE WITH RANDOM ACCESS MEMORY 有权
标题翻译：使用随机存取存储器的虚拟缓存
公开(公告)号：US20110078340A1
公开(公告)日：2011-03-31
申请号：US12567638
申请日：2009-09-25
申请人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
IPC分类号： G06F12/00 , G06F3/00 , G06F13/00
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译：降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。

75. 发明授权

US07571285B2 Data classification in shared cache of multiple-core processor 有权
标题翻译：多核处理器共享缓存中的数据分类
公开(公告)号：US07571285B2
公开(公告)日：2009-08-04
申请号：US11491043
申请日：2006-07-21
申请人： Christopher J. Hughes , Yen-Kuang Chen
发明人： Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定数据状态是否指示第一类数据的方法，基于该确定将数据从第二类重新分类为第一类，并将数据移动到基于重新分类，与第一请求者单元相关联的共享缓存的第一部分。描述和要求保护其他实施例。

76. 发明申请

US20090172243A1 Providing metadata in a translation lookaside buffer (TLB) 有权
标题翻译：在翻译后备缓冲区（TLB）中提供元数据
公开(公告)号：US20090172243A1
公开(公告)日：2009-07-02
申请号：US12005892
申请日：2007-12-28
申请人： David Champagne , Abhishek Tiwari , Wei Wu , Christopher J. Hughes , Sanjeev Kumar , Shih-Lien Lu
发明人： David Champagne , Abhishek Tiwari , Wei Wu , Christopher J. Hughes , Sanjeev Kumar , Shih-Lien Lu
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/1036 , G06F12/1009 , G06F12/1027 , G06F2212/681
摘要： In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括翻译后备缓冲器（TLB），用于存储每个具有翻译部分以存储虚拟地址（VA）至物理地址（PA）转换）的条目，以及存储用于存储器的位的第二部分与VA到PA转换相关联的页面，其中位指示存储器页面中的信息的属性。描述和要求保护其他实施例。

77. 发明授权

US07454576B2 System and method for cache coherency in a cache with different cache location lengths 失效
标题翻译：具有不同高速缓存位置长度的高速缓存中的高速缓存一致性的系统和方法
公开(公告)号：US07454576B2
公开(公告)日：2008-11-18
申请号：US11024278
申请日：2004-12-27
申请人： Yen-Kuang Chen , Christopher J. Hughes , James M. Tuck, III
发明人： Yen-Kuang Chen , Christopher J. Hughes , James M. Tuck, III
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F12/0817 , G06F12/0886 , Y10S707/99952
摘要： A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
摘要翻译：公开了一种用于在一级缓存中具有不同高速缓存位置长度的缓存系统的设计和操作的系统和方法。在一个实施例中，每个级别一个高速缓存可以包括不同长度的高速缓存位置组，能够保持二级高速缓存行的部分。状态树可以从共享向量中的数据创建。当请求从一级缓存到达时，二级缓存可以检查状态树的节点，以确定与进入请求相对应的状态树的节点是否已经是活动的。该确定的结果可以用于抑制或允许并发处理请求。

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