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71. 发明授权

US07994829B2 Fast lock-in all-digital phase-locked loop with extended tracking range 有权
标题翻译：快速锁定全数字锁相环，扩展跟踪范围
公开(公告)号：US07994829B2
公开(公告)日：2011-08-09
申请号：US12580556
申请日：2009-10-16
申请人： Hong-Yean Hsieh , Chao-Cheng Lee
发明人： Hong-Yean Hsieh , Chao-Cheng Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/113 , H03L7/091 , H03L7/099 , H03L2207/50
摘要： An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.
摘要翻译：公开了一种用于实现锁相环（PLL）锁定的装置和方法。 PLL接收参考时钟，并根据参考时钟产生输出时钟。该方法包括：通过以第二时钟周期的数量计数第一时钟的上升沿的数量来调节PLL的受控振荡器的振荡频率接近期望的频率; 通过临时改变数字控制振荡器的振荡频率，对准第三时钟的上升沿和第四时钟的上升沿; 以及通过PLL的相位检测器锁定第三和第四时钟的相位，其中第一和第三时钟对应于输出时钟，第二和第四时钟对应于参考时钟。

72. 发明授权

US07932847B1 Hybrid coarse-fine time-to-digital converter 有权
标题翻译：混合粗精细时间 - 数字转换器
公开(公告)号：US07932847B1
公开(公告)日：2011-04-26
申请号：US12631005
申请日：2009-12-04
申请人： Hong-Yean Hsieh , Chao-Cheng Lee
发明人： Hong-Yean Hsieh , Chao-Cheng Lee
IPC分类号： H03M1/12
CPC分类号： G04F10/005
摘要： A hybrid coarse-fine time-to-digital converter is disclosed. The hybrid coarse-fine time-to-digital converter is configured to receive a first input signal and a second input signal and to generate a digital output that corresponds to the time difference of between a rising edge of the first input signal and a rising edge of the second input signal. The hybrid coarse-fine time-to-digital converter comprises a coarse time-to-digital converter, a fine time-to-digital converter, and a correlated output generator.
摘要翻译：公开了一种混合粗细时间 - 数字转换器。混合粗细时间 - 数字转换器被配置为接收第一输入信号和第二输入信号，并且产生对应于第一输入信号的上升沿和上升沿之间的时间差的数字输出的第二输入信号。混合粗细时间 - 数字转换器包括粗略的时间 - 数字转换器，精细的时间 - 数字转换器和相关的输出发生器。

73. 发明授权

US07816971B2 Switch circuit having adjustable linearity of differential mode resistances 有权
标题翻译：开关电路具有可调整的差模电阻的线性度
公开(公告)号：US07816971B2
公开(公告)日：2010-10-19
申请号：US12245401
申请日：2008-10-03
申请人： Chao-Cheng Lee , Ren-Chieh Liu
发明人： Chao-Cheng Lee , Ren-Chieh Liu
IPC分类号： H03K17/16
CPC分类号： H03K5/003 , H03K17/145
摘要： A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.
摘要翻译：开关电路包括一对金属氧化物半导体（MOS）开关和调节单元。每个MOS开关具有输入端子和输出端子。 MOS开关在其输入端接收一对差分输入电压，并且当MOS开关导通时，在其输出端输出一对差分输出电压。调整单元改变输入端子的共模电平和MOS开关的输出端子之间的差异，以便调节MOS开关的差动模式电阻的线性度。

74. 再颁专利

USRE41598E1 Impedance matching circuit 有权
标题翻译：阻抗匹配电路
公开(公告)号：USRE41598E1
公开(公告)日：2010-08-31
申请号：US11108886
申请日：2005-04-19
申请人： Horng-Der Chang , Chao-Cheng Lee
发明人： Horng-Der Chang , Chao-Cheng Lee
IPC分类号： H03K19/003
CPC分类号： H04L25/0278
摘要： The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.
摘要翻译：本发明公开了一种阻抗匹配电路，用于促进电缆的特性阻抗与用于数据传输的接收机的输入端之间的输入阻抗之间的阻抗匹配，包括：第一晶体管，第二晶体管，电阻，负反馈控制电路，多路复用器和参考电压发生器。当电缆的特性阻抗变化时，阻抗匹配电路的等效电阻可以通过调整参考电压而保持等于电缆变化的特性阻抗的电阻。

75. 发明授权

US07636405B2 Apparatus and method for calibrating in-phase and quadrature-phase mismatch 有权
标题翻译：用于校准同相和正交相位失配的装置和方法
公开(公告)号：US07636405B2
公开(公告)日：2009-12-22
申请号：US10908109
申请日：2005-04-28
申请人： Chao-Cheng Lee , Ying-Yao Lin , Ying-Hsi Lin
发明人： Chao-Cheng Lee , Ying-Yao Lin , Ying-Hsi Lin
IPC分类号： H04L1/00
CPC分类号： H04B1/30 , H04B17/11
摘要： A method and device for calibrating in-phase and quadrature-phase (IQ) mismatch. The device is used in a direct down-conversion circuit of a communication system. The device has a first mixer for mixing an RF signal with a first carrier signal, so as to generate an in-phase analog signal; a second mixer for mixing the RF signal with a second carrier signal, so as to generate a quadrature-phase analog signal; an operation unit for executing a Least Mean Square (LMS) algorithm and thereby generating a compensation signal according to the in-phase analog signal and the quadrature-phase analog signal; and a calibration unit for compensating the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal, so as to calibrate the IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal.
摘要翻译：用于校准同相和正交相（IQ）失配的方法和装置。该设备用于通信系统的直接下变频电路。该装置具有用于混合RF信号与第一载波信号的第一混频器，以产生同相模拟信号; 第二混频器，用于将RF信号与第二载波信号混频，以产生正交相位模拟信号; 操作单元，用于执行最小均方（LMS）算法，从而根据同相模拟信号和正交相位模拟信号产生补偿信号; 以及校准单元，用于根据补偿信号补偿同相模拟信号和正交相位模拟信号，以便校准同相模拟信号和正交相位模拟信号之间的IQ失配。

76. 发明授权

US07560991B2 Dynamically compensated operational amplifier 有权
标题翻译：动态补偿运算放大器
公开(公告)号：US07560991B2
公开(公告)日：2009-07-14
申请号：US11674150
申请日：2007-02-13
申请人： Chia-Liang Lin , Gerchih Chou , Chao-Cheng Lee
发明人： Chia-Liang Lin , Gerchih Chou , Chao-Cheng Lee
IPC分类号： H03F1/14
CPC分类号： H03F1/086 , H03F1/3211 , H03F3/45183 , H03F2200/153 , H03F2203/45511 , H03F2203/45512 , H03F2203/45514
摘要： An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.
摘要翻译：运算放大器根据运算放大器的内部状态进行动态补偿。仅当内部状态表示不稳定的风险时，补偿才能完全启用。当运算放大器的内部状态表明不存在不稳定的风险时，补偿完全或部分关闭。

77. 发明授权

US07404094B2 Relay set in network device and method thereof 有权
标题翻译：网络设备中的中继集及其方法
公开(公告)号：US07404094B2
公开(公告)日：2008-07-22
申请号：US11308117
申请日：2006-03-07
申请人： Chao-Cheng Lee , Shian-Ru Lin
发明人： Chao-Cheng Lee , Shian-Ru Lin
IPC分类号： G06F1/00
CPC分类号： H04L12/66 , H03K17/693
摘要： A relay set in a network device. The relay includes a first switch, a switch control unit, and a first AC coupling unit. The first switch is coupled between a first receiving end of the network device and a first transmitting end of the network device. The switch control unit is configured to turn off the first switch when the network device is in a first state. The first AC coupling unit is configured to turn on the first switch according to a first signal received from the first receiving end when the network device is in a second state.
摘要翻译：在网络设备中设置的中继器。继电器包括第一开关，开关控制单元和第一AC耦合单元。第一交换机耦合在网络设备的第一接收端和网络设备的第一发送端之间。开关控制单元被配置为当网络设备处于第一状态时关闭第一交换机。第一AC耦合单元被配置为当网络设备处于第二状态时，根据从第一接收端接收到的第一信号来接通第一交换机。

78. 发明授权

US07378875B2 Compensation circuits for unequal input/output common mode voltages 有权
标题翻译：不等输入/输出共模电压的补偿电路
公开(公告)号：US07378875B2
公开(公告)日：2008-05-27
申请号：US11273026
申请日：2005-11-14
申请人： Chao-Cheng Lee , Tzung-Ming Chen
发明人： Chao-Cheng Lee , Tzung-Ming Chen
IPC分类号： H03K17/62
CPC分类号： H03F3/45479 , H03F3/45475 , H03F3/45968 , H03F3/45973
摘要： A circuit apparatus having compensation circuits for unequal input/output common mode voltages is presented. The apparatus includes a circuit unit, a feedback path and a current source. The circuit unit has at least an input terminal for receiving an input signal and at least an output terminal for generating an output signal. The input terminal configured to provide an input common mode voltage and the output terminal configured to provide an output common mode voltage. The feedback path couples the output terminal and the input terminal. The current source is coupled to the input terminal to supply a current. The voltage drop generated at the feedback path compensates the difference between the input common mode voltage and the output common mode voltage.
摘要翻译：提出了具有不等输入/输出共模电压的补偿电路的电路装置。该装置包括电路单元，反馈路径和电流源。电路单元至少具有用于接收输入信号的输入端子和至少一个用于产生输出信号的输出端子。输入端子被配置为提供输入共模电压，并且输出端子被配置为提供输出共模电压。反馈路径耦合输出端子和输入端子。电流源耦合到输入端以提供电流。在反馈路径处产生的电压降补偿输入共模电压和输出共模电压之间的差值。

79. 发明申请

US20080068071A1 VOLTAGE CONVERTING CIRCUIT STRUCTURE 有权
标题翻译：电压转换电路结构
公开(公告)号：US20080068071A1
公开(公告)日：2008-03-20
申请号：US11946879
申请日：2007-11-29
申请人： Chao-Cheng Lee
发明人： Chao-Cheng Lee
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： A voltage converting circuit is able to convert an input voltage generated by a system to a voltage capable of being utilized by a chip, avoids the defects of conventional switching regulators and linear regulators, and achieves voltage regulation with extremely high power efficiency and without off-chip components. The voltage converting circuit is adapted in systems with a plurality of similar or identical circuits.
摘要翻译：电压转换电路能够将由系统产生的输入电压转换为能够被芯片利用的电压，避免了传统的开关稳压器和线性稳压器的缺陷，并且以极高的功率效率和无关的电压来实现电压调节，芯片组件。电压转换电路适用于具有多个类似或相同电路的系统。

80. 发明申请

US20080058030A1 Transmitter for transmitting a transmission signal 有权
标题翻译：用于发送发送信号的发送器
公开(公告)号：US20080058030A1
公开(公告)日：2008-03-06
申请号：US11727101
申请日：2007-03-23
申请人： Chao-Cheng Lee
发明人： Chao-Cheng Lee
IPC分类号： H04B1/38
CPC分类号： H03F3/45206 , H03F1/0283 , H03F3/245 , H03F2200/451 , H03F2203/45028 , H03F2203/45511 , H03F2203/45638
摘要： A transmitter for transmitting a transmission signal is disclosed. The transmitter includes: a gain stage, for receiving an input signal and amplifying the input signal according to a gain to generate an amplified signal; and an output stage, coupled to the gain stage, for receiving a first reference voltage signal and the amplified signal and utilizing the first reference voltage signal to perform a predetermined operation on the amplified signal to generate the output signal.
摘要翻译：公开了用于发送发送信号的发送机。发射机包括：增益级，用于接收输入信号并根据增益放大输入信号以产生放大信号; 以及耦合到增益级的输出级，用于接收第一参考电压信号和放大信号，并利用第一参考电压信号对放大的信号执行预定的操作以产生输出信号。

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