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71. 发明授权

US07825451B2 Array of capacitors with electrically insulative rings 有权
标题翻译：具有电绝缘环的电容器阵列
公开(公告)号：US07825451B2
公开(公告)日：2010-11-02
申请号：US11787079
申请日：2007-04-12
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L29/76
CPC分类号： H01L27/0805 , H01L27/101 , H01L27/10808 , H01L27/10852 , H01L28/90 , H01L28/91
摘要： The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.
摘要翻译：本发明包括方法和集成电路。支柱从单个电容器存储节点位置的第一材料的开口向外突出。绝缘材料在突出柱的侧壁周围横向沉积在第一材料上，并且被各向异性蚀刻有效地暴露下面的第一材料并且留下横向于突出支柱的侧壁横向接收的电绝缘材料。开口形成在支柱的第二材料内。支柱通过第二材料中的开口从衬底上蚀刻出来，并且单独的电容器电极形成在与存储节点位置电连接的开口内。单独的电容器电极具有各向异性蚀刻的绝缘材料，其横向地围绕其外侧壁接收。各个电容器电极被并入到多个电容器中。考虑其他实现和方面。

72. 发明申请

US20100270641A1 Semiconductor Fuse Arrangements 有权
标题翻译：半导体保险丝安排
公开(公告)号：US20100270641A1
公开(公告)日：2010-10-28
申请号：US12832840
申请日：2010-07-08
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.
摘要翻译：本发明包括在多个导电连接件上并与之电接触的包含导电板的半导体熔丝装置。每个链接件相对于其它连接件与导电板接触作为一个单独的区域，并且链接件与导电板接触的区域是熔丝。本发明还包括形成半导体熔丝装置的方法。

73. 发明授权

US07737022B2 Contact formation 有权
标题翻译：接触层
公开(公告)号：US07737022B2
公开(公告)日：2010-06-15
申请号：US12401996
申请日：2009-03-11
申请人： James Mathew , H. Montgomery Manning
发明人： James Mathew , H. Montgomery Manning
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.
摘要翻译：本公开包括各种方法，电路，设备和系统实施例。一种这样的方法实施例包括在绝缘体堆叠材料中形成沟槽，其具有位于多个栅极中的两个之间的沟槽的一部分，并且将间隔物材料沉积到沟槽的至少一个侧表面。该方法还包括将导电材料沉积到沟槽中并将盖材料沉积到沟槽中。

74. 发明申请

US20100065941A1 INTERMEDIATE SEMICONDUCTOR STRUCTURES 有权
标题翻译：中间半导体结构
公开(公告)号：US20100065941A1
公开(公告)日：2010-03-18
申请号：US12622939
申请日：2009-11-20
申请人： David H. Wells , H. Montgomery Manning
发明人： David H. Wells , H. Montgomery Manning
IPC分类号： H01L29/06
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/76283
摘要： An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.
摘要翻译：公开了一种中间半导体结构，其包括衬底和形成在衬底中的至少一个底切结构。底切特征可以包括其中具有侧向空腔的垂直开口，垂直开口延伸到横向空腔下方。横向空腔可以包括刻面侧壁。

75. 发明申请

US20090286377A1 Methods of Forming Integrated Circuit Devices 有权
标题翻译：形成集成电路器件的方法
公开(公告)号：US20090286377A1
公开(公告)日：2009-11-19
申请号：US12512756
申请日：2009-07-30
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
摘要翻译：本发明包括形成半导体结构的方法和形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。在电极结构的外侧壁露出之后，去除保护盖。然后将电极结构并入电容器结构。

76. 发明申请

US20090176365A1 CONTACT FORMATION 有权
标题翻译：联系方式
公开(公告)号：US20090176365A1
公开(公告)日：2009-07-09
申请号：US12401996
申请日：2009-03-11
申请人： James Mathew , H. Montgomery Manning
发明人： James Mathew , H. Montgomery Manning
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.
摘要翻译：本公开包括各种方法，电路，设备和系统实施例。一种这样的方法实施例包括在绝缘体堆叠材料中形成沟槽，其具有位于多个栅极中的两个之间的沟槽的一部分，并且将间隔物材料沉积到沟槽的至少一个侧表面。该方法还包括将导电材料沉积到沟槽中并将盖材料沉积到沟槽中。

77. 发明申请

US20090173982A1 METHOD FOR FORMING MEMORY CELL AND DEVICE 有权
标题翻译：形成记忆细胞和装置的方法
公开(公告)号：US20090173982A1
公开(公告)日：2009-07-09
申请号：US12405574
申请日：2009-03-17
申请人： H. Montgomery Manning , David H. Wells
发明人： H. Montgomery Manning , David H. Wells
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译：存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

78. 发明授权

US07534694B2 Methods of forming a plurality of capacitors 失效
标题翻译：形成多个电容器的方法
公开(公告)号：US07534694B2
公开(公告)日：2009-05-19
申请号：US11477957
申请日：2006-06-28
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on a second pair of opposing sides by a different second capacitor electrode-forming material at the one elevation. Individual capacitor electrodes are formed within individual of the capacitor electrode openings. The capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成多个电容器的方法。在一个实施方案中，在衬底上形成多个电容器电极开口。电容器电极开口的个体在一个高度上由第一对电容器电极形成材料限定在第一对相对侧上，并且在一个高度处由不同的第二电容器电极形成材料限定在第二对相对侧上。单个电容器电极形成在电容器电极开口的单独内部。电容器电极被并入多个电容器中。考虑了其他方面和实现。

79. 发明授权

US07387939B2 Methods of forming semiconductor structures and capacitor devices 有权
标题翻译：形成半导体结构和电容器器件的方法
公开(公告)号：US07387939B2
公开(公告)日：2008-06-17
申请号：US10894633
申请日：2004-07-19
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.
摘要翻译：本发明包括形成半导体结构的方法和形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。在电极结构的外侧壁露出之后，去除保护盖。然后将电极结构并入电容器结构。

80. 发明授权

US07306991B2 Stepped gate configuration for non-volatile memory 有权
标题翻译：非易失性存储器的步进门配置
公开(公告)号：US07306991B2
公开(公告)日：2007-12-11
申请号：US11257636
申请日：2005-10-25
申请人： H. Montgomery Manning , Kunal Parekh
发明人： H. Montgomery Manning , Kunal Parekh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.
摘要翻译：本文公开了具有带梯级栅极电介质的场效应晶体管及其制造方法的存储器件。阶梯式栅极电介质形成在半导体衬底上，由一对由栅极电介质隔开的电荷俘获电介质组成; 在其上形成栅极导体。源极和漏极区域形成在该对电荷俘获电介质的相对侧上的半导体衬底中。存储器件通过在半导体衬底上形成电荷俘获电介质层而制成。通过电荷捕获电介质层形成沟槽以暴露半导体衬底的一部分。栅极电介质层形成在沟槽内，栅极导体层形成在电荷俘获和栅极电介质层上。

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