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71. 发明申请

US20070194294A1 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070194294A1
公开(公告)日：2007-08-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L29/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

72. 发明授权

US07205199B2 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US07205199B2
公开(公告)日：2007-04-17
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

73. 发明申请

US20070063247A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070063247A1
公开(公告)日：2007-03-22
申请号：US11450269
申请日：2006-06-12
申请人： Yeol Jon , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Yeol Jon , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10852
摘要： Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.
摘要翻译：提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

74. 发明申请

US20070026685A1 Mask structure, method of forming the mask structure, method of forming a pattern using the mask structure and method of forming contacts in a semiconductor device using the mask structure 审中-公开
标题翻译：掩模结构，形成掩模结构的方法，使用掩模结构形成图案的方法以及使用掩模结构在半导体器件中形成接触的方法
公开(公告)号：US20070026685A1
公开(公告)日：2007-02-01
申请号：US11481177
申请日：2006-07-06
申请人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
发明人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least two openings that expose portions of the object adjacent to sides of the first mask pattern. Because the mask structure has the first and the second mask patterns, desired structures, for example, recesses, trenches, contact holes or patterns may be more precisely formed on or through the object. For example, the first mask pattern may protect the object in an etching process for forming contact holes so that the contact holes may not be connected to each other, for example, when the contact holes have bar shapes or line shapes.
摘要翻译：掩模结构可以包括形成在物体上的第一掩模图案和第二掩模图案。当物体包括第一材料时，第一和第二掩模图案可以分别包括第二材料和第三材料。第二掩模图案可以具有暴露邻近第一掩模图案的侧面的物体的部分的至少两个开口。由于掩模结构具有第一和第二掩模图案，所以可以更精确地形成所需的结构，例如凹槽，沟槽，接触孔或图案。例如，第一掩模图案可以在用于形成接触孔的蚀刻工艺中保护物体，使得接触孔可以不彼此连接，例如当接触孔具有条形或线形时。

75. 发明申请

US20070012906A1 Phase-change semiconductor device and methods of manufacturing the same 有权
标题翻译：相变半导体器件及其制造方法
公开(公告)号：US20070012906A1
公开(公告)日：2007-01-18
申请号：US11482760
申请日：2006-07-10
申请人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
发明人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.
摘要翻译：在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻停止层与基底形成电连接。

76. 发明申请

US20060189126A1 Method of forming semiconductor device having epitaxial contact plug connecting stacked transistors 审中-公开
标题翻译：形成具有连接堆叠晶体管的外延接触插塞的半导体器件的方法
公开(公告)号：US20060189126A1
公开(公告)日：2006-08-24
申请号：US11269602
申请日：2005-11-09
申请人： Ki-Hoon Jang , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Ki-Hoon Jang , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684
摘要： A method of forming an epitaxial contact plug in a semiconductor device comprises forming an insulating interlayer on a semiconductor substrate, forming a mushroom-shaped epitaxial plug in an opening of the insulating interlayer, forming a buffer layer on the epitaxial plug and the insulating interlayer, and planarizing epitaxial plug and the insulating interlayer using a chemical mechanical polishing (CMP) process.
摘要翻译：在半导体器件中形成外延接触插塞的方法包括在半导体衬底上形成绝缘中间层，在绝缘中间层的开口中形成蘑菇形外延塞，在外延插塞和绝缘中间层上形成缓冲层，并使用化学机械抛光（CMP）工艺平面化外延塞和绝缘夹层。

77. 发明申请

US20050077568A1 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US20050077568A1
公开(公告)日：2005-04-14
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/76 , H01L21/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

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