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71. 发明申请

US20070296001A1 MULTIPLE CONDUCTION STATE DEVICES HAVING DIFFERENTLY STRESSED LINERS 失效
标题翻译：具有不同应力衬层的多个导电状态器件
公开(公告)号：US20070296001A1
公开(公告)日：2007-12-27
申请号：US11425511
申请日：2006-06-21
申请人： Dureseti Chidambarrao , David M. Onsongo
发明人： Dureseti Chidambarrao , David M. Onsongo
IPC分类号： H01L29/768
CPC分类号： H01L29/7833 , H01L21/823412 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
摘要翻译：提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

72. 发明申请

US20070275532A1 OPTIMIZED DEEP SOURCE/DRAIN JUNCTIONS WITH THIN POLY GATE IN A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：优化的深度源/漏极结与场效应晶体管中的多晶栅
公开(公告)号：US20070275532A1
公开(公告)日：2007-11-29
申请号：US11420053
申请日：2006-05-24
申请人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
发明人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.
摘要翻译：提供了其中减少多晶硅栅极的多晶硅耗尽和寄生电容问题的半导体结构及其制造方法。该结构包括薄多晶硅栅极和优化的深源极/漏极掺杂。该方法改变了不同植入步骤的顺序，并且使得可以制造结构而没有剂量损失或掺杂渗透问题。根据本发明，牺牲硬掩模覆盖层用于阻挡高能量注入，并且使用3-1间隔物（偏置间隔物，第一间隔物和第二间隔物）方案来优化源极/漏极掺杂分布。通过这种方法，可以增加注入薄多晶硅栅极的剂量，同时可以优化深源/漏植入，而不用担心渗透问题。

73. 发明申请

US20070249126A1 A STRUCTURE AND METHOD FOR FABRICATION OF DEEP JUNCTION SILICON-ON-INSULATOR TRANSISTORS 失效
标题翻译：一种用于制造深层结晶硅绝缘体晶体管的结构和方法
公开(公告)号：US20070249126A1
公开(公告)日：2007-10-25
申请号：US11308685
申请日：2006-04-21
申请人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
发明人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823814
摘要： A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.
摘要翻译：提供一种用于制造晶体管结构的结构和方法。该方法包括以下步骤：（a）提供包括绝缘体上半导体（“SOI”）层的衬底，该衬底通过掩埋电介质层与衬底的主体区域分离。（b）首先注入SOI层以在SOI层与掩埋介电层的界面处实现预定的掺杂剂浓度。以及（c）第二次注入所述SOI层以在多晶半导体栅极导体（“多晶硅”）中以及在与所述多晶硅栅极相邻设置的源极和漏极区域中实现预定的掺杂剂浓度，其中所述第一注入的最大深度大于第二次植入的最大深度。

74. 发明申请

US20070158753A1 SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE 失效
标题翻译：具有相同基板上的相同导电类型的低性能和高性能器件的半导体器件结构
公开(公告)号：US20070158753A1
公开(公告)日：2007-07-12
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

75. 发明申请

US20070122956A1 TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION 失效
标题翻译：具有完全基于主动半导体区域的电介质压电元件的晶体管
公开(公告)号：US20070122956A1
公开(公告)日：2007-05-31
申请号：US11164632
申请日：2005-11-30
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L21/8234 , H01L31/00 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/26513 , H01L21/31675 , H01L21/823807 , H01L21/823878 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654
摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.
摘要翻译：压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

76. 发明授权

US07224021B2 MOSFET with high angle sidewall gate and contacts for reduced miller capacitance 有权
标题翻译：具有高角度侧壁栅极的MOSFET和用于降低铣刀电容的触点
公开(公告)号：US07224021B2
公开(公告)日：2007-05-29
申请号：US11162424
申请日：2005-09-09
申请人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
发明人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7836 , H01L21/26586 , H01L21/28518 , H01L21/76804 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
摘要翻译：本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面区。与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

77. 发明申请

US20070108531A1 ROTATIONAL SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION 有权
标题翻译：充电移动机动车修改的旋转剪应力
公开(公告)号：US20070108531A1
公开(公告)日：2007-05-17
申请号：US11164179
申请日：2005-11-14
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L29/76
CPC分类号： H01L21/76229 , H01L29/517 , H01L29/665 , H01L29/66575 , H01L29/7833 , H01L29/7846
摘要： A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.
摘要翻译：半导体结构及其制造方法利用具有由隔离沟槽包围的有源区域台面的半导体衬底。具有第一应力的第一隔离区域位于隔离沟槽中。具有不同于第一应力的第二应力的第二隔离区也位于隔离沟槽中。第一隔离区域和第二隔离区域的尺寸和尺寸被设置成对活性区域台面进行旋转剪切应力。

78. 发明申请

US20070096215A1 TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENTS 失效
标题翻译：具有介质压力元件的晶体管
公开(公告)号：US20070096215A1
公开(公告)日：2007-05-03
申请号：US11163683
申请日：2005-10-27
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823412 , H01L29/0653 , H01L29/7846
摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.
摘要翻译：提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。

79. 发明申请

US20070096206A1 GATE ELECTRODE STRESS CONTROL FOR FINFET PERFORMANCE ENHANCEMENT 有权
标题翻译：用于FINFET性能增强的门电极应力控制
公开(公告)号：US20070096206A1
公开(公告)日：2007-05-03
申请号：US11163908
申请日：2005-11-03
申请人： Dureseti Chidambarrao
发明人： Dureseti Chidambarrao
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.
摘要翻译： finFET及其制造方法包括形成在半导体鳍片的沟道区域上的栅电极。半导体鳍具有晶体取向和轴向特定的压阻系数。形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向特定的压阻系数相匹配的感应的轴向应力。

80. 发明授权

US07198995B2 Strained finFETs and method of manufacture 有权
标题翻译：应变finFET和制造方法
公开(公告)号：US07198995B2
公开(公告)日：2007-04-03
申请号：US10733378
申请日：2003-12-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。

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