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71. 发明授权

US07934110B2 Dynamically managing thermal levels in a processing system 有权
标题翻译：在处理系统中动态管理热水平
公开(公告)号：US07934110B2
公开(公告)日：2011-04-26
申请号：US11861186
申请日：2007-09-25
申请人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
发明人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
IPC分类号： G06F1/26 , G06F1/22
CPC分类号： G06F1/206 , G05D23/1935
摘要： A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.
摘要翻译：通过采用节流技术的交错核心跳跃来动态地维持处理系统的多个核心的热水平的技术。如果核心跳跃可应用，交错逻辑可以将线程的执行从热核心转移到冷。如果存在可以从热核心分配线程的执行的冷核心以及核心跳跃的发生速率在可允许的速率值内的情况下，可以应用核心跳频。如果核心跳频不适用，交错逻辑可以应用节流技术。节流技术可以节流节流参数，其可以包括提供给热核心的电压，频率和微架构节流参数，如果核心跳频不适用。

72. 发明申请

US20090083551A1 DYNAMICALLY MANAGING THERMAL LEVELS IN A PROCESSING SYSTEM 有权
标题翻译：在处理系统中动态地管理热水平
公开(公告)号：US20090083551A1
公开(公告)日：2009-03-26
申请号：US11861186
申请日：2007-09-25
申请人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
发明人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
IPC分类号： G05D23/00 , G06F1/00
CPC分类号： G06F1/206 , G05D23/1935
摘要： A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.
摘要翻译：通过采用节流技术的交错核心跳跃来动态地维持处理系统的多个核心的热水平的技术。如果核心跳跃可应用，交错逻辑可以将线程的执行从热核心转移到冷。如果存在可以从热核心分配线程的执行的冷核心以及核心跳跃的发生速率在可允许的速率值内的情况下，可以应用核心跳频。如果核心跳频不适用，交错逻辑可以应用节流技术。节流技术可以节流节流参数，其可以包括提供给热核心的电压，频率和微架构节流参数，如果核心跳频不适用。

73. 发明申请

US20080148027A1 Method and apparatus of power managment of processor 有权
标题翻译：处理器功率管理方法与装置
公开(公告)号：US20080148027A1
公开(公告)日：2008-06-19
申请号：US11638700
申请日：2006-12-14
申请人： Russell J. Fenger , Anil Aggarwal , Efraim Rotem
发明人： Russell J. Fenger , Anil Aggarwal , Efraim Rotem
IPC分类号： G06F9/06
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.
摘要翻译：简而言之，是一种处理器和一种设置turbo模式使能处理器的性能状态的方法。该方法包括在预定时间段内确定有效性能状态，在预定时间段内基于核心利用率和有效性能状态计算目标性能状态，并将启用turbo模式的处理器设置为turbo模式执行状态。

74. 发明申请

US20130283032A1 COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT 审中-公开
标题翻译：协同处理器和系统性能和电源管理
公开(公告)号：US20130283032A1
公开(公告)日：2013-10-24
申请号：US13977531
申请日：2011-12-30
申请人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem
发明人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem
IPC分类号： G06F9/44 , G06F1/32
CPC分类号： G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
摘要翻译：本发明涉及一种平台电源管理方案。在一些实施例中，平台使用OSPM系统请求的一个或多个参数来提供相对性能量表。

75. 发明授权

US07818596B2 Method and apparatus of power management of processor 有权
标题翻译：处理器电源管理方法及装置
公开(公告)号：US07818596B2
公开(公告)日：2010-10-19
申请号：US11638700
申请日：2006-12-14
申请人： Russell J. Fenger , Anil Aggarwal , Efraim Rotem
发明人： Russell J. Fenger , Anil Aggarwal , Efraim Rotem
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.
摘要翻译：简而言之，是一种处理器和一种设置turbo模式使能处理器的性能状态的方法。该方法包括在预定时间段内确定有效性能状态，在预定时间段内基于核心利用率和有效性能状态计算目标性能状态，并将启用turbo模式的处理器设置为turbo模式执行状态。

76. 发明授权

US10108433B2 Collaborative processor and system performance and power management 有权
公开(公告)号：US10108433B2
公开(公告)日：2018-10-23
申请号：US13977531
申请日：2011-12-30
申请人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem
发明人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem
IPC分类号： G06F1/32 , G06F9/44 , G06F9/4401 , G06F17/30 , G06F9/445 , G06F1/28 , G06F11/36 , G06F1/26 , G06F9/22 , G06F11/30 , G06F11/34 , G06F9/30 , G06F1/20 , G06F15/78 , G06F9/38
摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

77. 发明授权

US09753516B2 Method, apparatus, and system for energy efficiency and energy conservation by mitigating performance variations between integrated circuit devices 有权
公开(公告)号：US09753516B2
公开(公告)日：2017-09-05
申请号：US13335628
申请日：2011-12-22
申请人： Ryan D. Wells , Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Gary A. Andrew
发明人： Ryan D. Wells , Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Gary A. Andrew
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3206 , G06F1/324 , Y02D10/126
摘要： According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

78. 发明申请

US20140380081A1 Restricting Clock Signal Delivery In A Processor 有权
标题翻译：限制处理器中的时钟信号传递
公开(公告)号：US20140380081A1
公开(公告)日：2014-12-25
申请号：US13925986
申请日：2013-06-25
申请人： Alexander Gendler , Efraim Rotem , Julius Mandelblat , Alexander Lyakhov , Larisa Novakovsky , George Leifman , Lev Makovsky , Ariel Sabba , Niv Tokman
发明人： Alexander Gendler , Efraim Rotem , Julius Mandelblat , Alexander Lyakhov , Larisa Novakovsky , George Leifman , Lev Makovsky , Ariel Sabba , Niv Tokman
IPC分类号： G06F1/08
CPC分类号： G06F1/08 , G06F1/04 , G06F1/32
摘要： In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑的第一时钟信号发送到多个单元中的至少一个。限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。描述和要求保护其他实施例。

79. 发明申请

US20140006808A1 EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATOR 有权
标题翻译：高效集成开关电压调节器
公开(公告)号：US20140006808A1
公开(公告)日：2014-01-02
申请号：US13538262
申请日：2012-06-29
申请人： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
发明人： Gregory Sizikov , Michael Zelikson , Efraim Rotem , Eyal Fayneh
IPC分类号： G06F1/26 , G05F3/08
CPC分类号： G06F1/324 , G05F3/08 , G06F1/26 , G06F1/32 , G06F1/3275 , H02M3/158
摘要： Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
摘要翻译：这里描述的集成电路包括：具有一个或多个桥式驱动器的开关电压调节器（SVR），以向多个电源域提供稳定的电源; 以及功率控制单元（PCU），其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率，其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元当SVR的开关频率被调整时。

80. 发明授权

US08539269B2 Apparatus and method for high current protection 有权
标题翻译：高电流保护装置及方法
公开(公告)号：US08539269B2
公开(公告)日：2013-09-17
申请号：US13077618
申请日：2011-03-31
申请人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Kosta Luria , Ronny Korner , Dan Baum
发明人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Kosta Luria , Ronny Korner , Dan Baum
IPC分类号： G06F1/32
CPC分类号： G06F1/30 , G06F1/28 , G06F1/3243 , G06F11/004 , G06F11/3024 , G06F11/3058 , G06F11/348 , G06F2201/81 , G06F2201/86 , Y02D10/152
摘要： An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.
摘要翻译：设备可以包括处理器的一个或多个处理器核心和一组限流器。每个限流器可以耦合到相应的处理器核心并且被布置成监视处理器中的处理器活动，以将处理器活动与多个电流限制的一个或多个电流限制进行比较; 并且当超过一个或多个电流限制时启动限流动作。

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