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71. 发明授权

US08344425B2 Multi-gate III-V quantum well structures 有权
标题翻译：多栅III-V量子阱结构
公开(公告)号：US08344425B2
公开(公告)日：2013-01-01
申请号：US12655463
申请日：2009-12-30
申请人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
发明人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
IPC分类号： H01L29/12 , H01L21/20 , H01L21/336 , H01L21/18
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。

72. 发明申请

US20120168877A1 METHOD TO REDUCE CONTACT RESISTANCE OF N-CHANNEL TRANSISTORS BY USING A III-V SEMICONDUCTOR INTERLAYER IN SOURCE AND DRAIN 有权
标题翻译：通过在源和漏极中使用III-V半导体中间层来降低N沟道晶体管的接触电阻的方法
公开(公告)号：US20120168877A1
公开(公告)日：2012-07-05
申请号：US12982083
申请日：2010-12-30
申请人： Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Robert S. Chau , Matthew V. Metz
发明人： Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Robert S. Chau , Matthew V. Metz
IPC分类号： H01L29/78 , H01L21/205 , H01L21/203
CPC分类号： H01L21/28575 , H01L29/66446
摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.
摘要翻译：通常使用通过在源极和漏极中使用III-V半导体夹层来降低n沟道晶体管的接触电阻的方法。在这方面，引入一种器件，其包括具有源极区和漏极区的n型晶体管，与晶体管相邻的第一层间电介质层，穿过第一层间介质层到源极区的沟槽，以及导电源接触沟槽，源极触点通过III-V半导体夹层与源极区分离。还公开并要求保护其他实施例。

73. 发明申请

US20110147798A1 CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES 有权
标题翻译： III-V半导体器件的电导率改进
公开(公告)号：US20110147798A1
公开(公告)日：2011-06-23
申请号：US12646711
申请日：2009-12-23
申请人： Marko Radosavljevic , Prashant Majhi , Jack T. Kavalieros , Niti Goel , Wilman Tsai , Niloy Mukherjee , Yong Ju Lee , Gilbert Dewey , Willy Rachmady
发明人： Marko Radosavljevic , Prashant Majhi , Jack T. Kavalieros , Niti Goel , Wilman Tsai , Niloy Mukherjee , Yong Ju Lee , Gilbert Dewey , Willy Rachmady
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7786 , H01L21/2256 , H01L29/20 , H01L29/42316 , H01L29/47 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
摘要翻译：描述了III-V半导体器件的电导率改进。第一改进包括与通道层不共同平面的阻挡层。第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

74. 发明申请

US20140103294A1 TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：对集成电路设备进行驱动的技术和配置
公开(公告)号：US20140103294A1
公开(公告)日：2014-04-17
申请号：US14106556
申请日：2013-12-13
申请人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
发明人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7782 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7848
摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。集成电路器件包括半导体衬底，与半导体衬底耦合的量子阱沟道，与量子阱沟道耦合的源极结构，与量子阱沟道耦合的漏极结构以及直接接触的应变诱导膜其中源结构和漏极结构的材料通过在量子阱沟道上施加拉伸或压缩应变来降低量子阱沟道的电阻，其中量子阱沟道设置在应变诱导膜和半导体衬底之间。可以描述和/或要求保护其他实施例。

75. 发明授权

US08324661B2 Quantum well transistors with remote counter doping 有权
标题翻译：具有远程反相掺杂的量子阱晶体管
公开(公告)号：US08324661B2
公开(公告)日：2012-12-04
申请号：US12646589
申请日：2009-12-23
申请人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
发明人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
IPC分类号： H01L21/338 , H01L29/66
CPC分类号： H01L29/66636 , H01L29/66462 , H01L29/7783 , H01L29/7784
摘要： A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.
摘要翻译：公开了一种量子阱器件及其制造方法。在一个实施例中，量子阱结构包括覆盖在衬底上的量子阱区域和包括与量子阱区域的电荷载流子的导电性相反的导电性的掺杂剂的远程计数器掺杂。远程计数器掺杂被结合在量子阱区域附近，用于与量子阱沟道交换移动载流子，从而减小截止状态的漏电流。在另一个实施例中，量子阱器件包括量子阱结构，其包括远程反相掺杂，覆盖量子阱结构的一部分的栅极区域和与栅极区域相邻的源极和漏极区域。量子阱器件还可以包括包含与量子阱沟道相同导电性的掺杂剂的远程δ掺杂。

76. 发明申请

US20110156004A1 Multi-gate III-V quantum well structures 有权
标题翻译：多栅III-V量子阱结构
公开(公告)号：US20110156004A1
公开(公告)日：2011-06-30
申请号：US12655463
申请日：2009-12-30
申请人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
发明人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
IPC分类号： H01L29/775 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。

77. 发明申请

US20130146845A1 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 有权
标题翻译：形成量子阱晶体管的技术
公开(公告)号：US20130146845A1
公开(公告)日：2013-06-13
申请号：US13758974
申请日：2013-02-04
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radiosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radiosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/775
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

78. 发明授权

US09099490B2 Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation 有权
标题翻译：用于非对称GaN晶体管的自对准结构和方法以及增强模式操作
公开(公告)号：US09099490B2
公开(公告)日：2015-08-04
申请号：US13631534
申请日：2012-09-28
申请人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Niti Goel , Sanaz Kabehie , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Niti Goel , Sanaz Kabehie , Seung Hoon Sung , Ravi Pillarisetty , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/778 , H01L29/423 , H01L29/08 , H01L29/20
CPC分类号： H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
摘要翻译：实施例包括高电子迁移率晶体管（HEMT）。在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

79. 发明授权

US09583574B2 Epitaxial buffer layers for group III-N transistors on silicon substrates 有权
标题翻译：在硅衬底上的III-N晶体管的外延缓冲层
公开(公告)号：US09583574B2
公开(公告)日：2017-02-28
申请号：US13631514
申请日：2012-09-28
申请人： Sansaptak Dasgupta , Han Wui Then , Niloy Mukherjee , Marko Radosavljevic , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Niloy Mukherjee , Marko Radosavljevic , Robert S. Chau
IPC分类号： H01L29/20 , H01L29/205 , H01L29/66 , H01L29/778 , H01L29/423
CPC分类号： H01L29/7787 , H01L23/535 , H01L29/04 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/66545
摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.
摘要翻译：实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

80. 发明申请

US20140158976A1 III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES 审中-公开
标题翻译： III-N硅半导体结构和技术
公开(公告)号：US20140158976A1
公开(公告)日：2014-06-12
申请号：US13706473
申请日：2012-12-06
申请人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L21/36 , H01L29/06
CPC分类号： H01L29/0684 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0262 , H01L21/02631 , H01L21/02642 , H01L21/02647 , H01L29/2003 , Y10S977/762
摘要： III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.
摘要翻译：公开了III-N半导体硅集成电路结构和技术。在一些情况下，该结构包括在成核层上形成的第一半导体层，第一半导体层在成核层上包含3-D GaN层并具有多个3-D半导体结构，以及2-D GaN层在3-D GaN层上。该结构还可以包括形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括二维GaN层上的AlGaN和AlGaN层上的GaN层。另一种结构包括形成在成核层上的第一半导体层，第一半导体层包括成核层上的2-D GaN层，以及形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括AlGaN 在2-D GaN层和AlGaN层上的GaN层。

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