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71. 发明申请

US20060258109A1 DRAM cells with vertical transistors 有权
公开(公告)号：US20060258109A1
公开(公告)日：2006-11-16
申请号：US11490294
申请日：2006-07-20
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

72. 发明申请

US20060226465A1 Concentric or nested container capacitor structure for integrated circuits 审中-公开
公开(公告)号：US20060226465A1
公开(公告)日：2006-10-12
申请号：US11449449
申请日：2006-06-07
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L27/10855
摘要： Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.

73. 发明授权

US07067880B2 Transistor gate structure 有权
标题翻译：晶体管门结构
公开(公告)号：US07067880B2
公开(公告)日：2006-06-27
申请号：US10673362
申请日：2003-09-30
申请人： Werner Juengling , Richard H. Lane
发明人： Werner Juengling , Richard H. Lane
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/28052 , H01L21/28061 , H01L29/4941 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.
摘要翻译：本发明教导了一种形成具有硅化物栅的MOSFET晶体管的方法，其在形成栅极堆叠结构时不会产生通过蚀刻含金属层产生的问题。在包括栅极氧化物层，导电层和第一绝缘层的半导体衬底上形成栅堆叠。侧壁间隔件形成在栅堆叠结构的侧面附近，并且第三绝缘层形成在栅堆叠和衬底上。去除第三绝缘层和第一绝缘层以暴露导电层，并且至少一个未蚀刻的含金属层形成在导电层上并与导电层接触。然后，栅极堆叠结构经历不同变化的硅化处理，最终形成硅化物栅极。

74. 发明申请

US20060024933A1 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry 有权
公开(公告)号：US20060024933A1
公开(公告)日：2006-02-02
申请号：US11236115
申请日：2005-09-26
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/38
CPC分类号： H01L27/10873 , H01L21/266 , H01L21/31116 , H01L21/31144 , H01L27/10894 , H01L29/6653
摘要： Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.

75. 发明授权

US06949430B2 Semiconductor processing methods 失效
标题翻译：半导体加工方法
公开(公告)号：US06949430B2
公开(公告)日：2005-09-27
申请号：US10851616
申请日：2004-05-20
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/311 , H01L21/8242
CPC分类号： H01L27/10873 , H01L21/266 , H01L21/31116 , H01L21/31144 , H01L27/10894 , H01L29/6653
摘要： Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
摘要翻译：描述了形成集成电路，特别是动态随机存取存储器（DRAM）电路的半导体处理方法。在一个实施例中，使用单个掩蔽步骤在衬底上形成掩模开口，并且提供两种杂质，并且通过开口蚀刻衬底的材料。在一个实施方案中，在要设置杂质的衬底区域上的光掩模层中以及要进行蚀刻的其它区域同时形成开口。在单独的步骤中，衬底掺杂有杂质，并且通过掩模开口蚀刻衬底的材料。在另一实施方式中，在衬底上形成两条导线，并且在导电线上形成掩模层。在相同步骤中的掩模层中形成开口，其中一个开口被接纳在一个导电线上，另一个开口被接收在另一个导线上。杂质通过靠近一根导电线路的衬底提供到衬底中，并且来自另一导电线的材料通过另一个开口去除，以至少部分地在另一个导电线上形成接触开口。

76. 发明授权

US06898779B2 Pattern generation on a semiconductor surface 有权
标题翻译：半导体表面上的图案生成
公开(公告)号：US06898779B2
公开(公告)日：2005-05-24
申请号：US10232853
申请日：2002-08-28
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： G03F1/00 , G03F1/36 , G06F9/45 , G06F9/455 , G06F17/50 , G06F19/00 , G06K9/46 , G21K5/00 , H01L21/4763
CPC分类号： G03F1/36 , G03F1/70
摘要： A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium such as computer software to interconnect a number of active areas on the wafer. The pattern is then modified according to a number of rules to create a pattern where substantially all spaces between planned elements exhibit a desired gap width. Layers of elements such as trace lines can be better covered with an ILD in a simplified deposition process as a result of the novel pattern formation described herein.
摘要翻译：示出了形成元件图案的方法。在一个实施例中，该方法用于创建掩模版。在另一个实施例中，该方法用于在半导体晶片的表面上进一步形成多个元件。首先使用诸如计算机软件的介质产生掩模版上的图案，以将晶片上的多个有效区域互连。然后根据许多规则修改图案以创建图案，其中计划元素之间基本上所有的空间呈现期望的间隙宽度。作为本文所述的新型图案形成的结果，诸如痕迹线的元件层可以在简化的沉积工艺中用ILD更好地覆盖。

77. 发明申请

US20050034092A1 Method and apparatus for designing a pattern on a semiconductor surface 有权
标题翻译：用于在半导体表面上设计图案的方法和装置
公开(公告)号：US20050034092A1
公开(公告)日：2005-02-10
申请号：US10931361
申请日：2004-08-31
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068
摘要： A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. Identified problem structures or regions in a pattern of elements are moved from lower level cells of a hierarchy structure into higher level cells before edge movement takes place. Because all cells have been selectively leveled first, substantially all external influences to cells have been removed for each cell before edge movement takes place. The methods and procedures described herein therefore reduce the possibility of undesirable modifications such as electrical shorts. The methods and procedures described herein also reduce overall processing time.
摘要翻译：示出了形成元件图案的方法。在一个实施例中，该方法用于创建掩模版。在另一个实施例中，该方法用于在半导体晶片的表面上进一步形成多个元件。识别的问题结构或元素模式中的区域在发生边缘移动之前从层次结构的较低级别单元移动到更高级别的单元格中。因为所有细胞首先被选择性地平整，所以在发生边缘移动之前，已经为每个细胞去除了对细胞的所有外部影响。因此，本文所述的方法和步骤减少了诸如电短路的不期望的修改的可能性。本文描述的方法和程序还减少了总体处理时间。

78. 发明授权

US06812160B2 Methods of forming materials between conductive electrical components, and insulating materials 失效
标题翻译：在导电电气部件和绝缘材料之间形成材料的方法
公开(公告)号：US06812160B2
公开(公告)日：2004-11-02
申请号：US09976624
申请日：2001-10-12
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L2131
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.
摘要翻译：在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

79. 发明授权

US06777813B2 Fill pattern generation for spin-on-glass and related self-planarization deposition 有权
标题翻译：填充图案生成用于旋涂玻璃和相关的自平坦化沉积
公开(公告)号：US06777813B2
公开(公告)日：2004-08-17
申请号：US10032877
申请日：2001-10-24
申请人： Werner Juengling , Philip J. Ireland
发明人： Werner Juengling , Philip J. Ireland
IPC分类号： H01L2348
CPC分类号： H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.
摘要翻译：用于诸如存储器单元的半导体器件的填充图案。存储单元包括多个第一地形结构，其包括沉积在半导体衬底上的导电引线，以及多个第二地形结构，其包括填充图案，使得第二地形结构的顶表面与多个顶部表面大致共面的第一个地形结构。多个第一和第二地形结构以基本上重复的阵列布置在基底上。平坦化层沉积在基板的顶部上，使得其填充多个第一和第二地形结构之间的空间，其顶表面与第一和第二地形结构的顶表面的顶表面大致共面。

80. 发明授权

US06777297B2 Disposable spacer and method of forming and using same 失效
标题翻译：一次性间隔物及其形成和使用方法
公开(公告)号：US06777297B2
公开(公告)日：2004-08-17
申请号：US10218825
申请日：2002-08-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/32105 , H01L21/32135 , H01L21/76216 , H01L21/8238 , H01L29/6656
摘要： A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. A method of forming the disposal spacer includes providing a device structure and forming a layer of germanium-silicon alloy on the device structure. The layer is then etched to form the disposable spacer. The device structure may include a substrate and a gate structure with the disposable spacers formed at sidewalls thereof. Further, the device structure may include a substrate having an oxidation mask formed thereon with the disposable spacers formed relative to sidewalls of the oxidation mask. In addition, the method includes removing the disposable spacer by oxidizing the spacer to form volatile GexSiyO. Any unvolatilized GexSiyO may be removed using water. Further, the removal step may be performed using a cleaning solution including ammonium hydroxide.
摘要翻译：用于半导体器件制造工艺的一次性间隔件由锗 - 硅合金形成。锗 - 硅合金可以包括锗的第一部分（x）和硅的第二部分（1-x），其中x大于约0.2。形成处置间隔物的方法包括在器件结构上提供器件结构并形成锗 - 硅合金层。然后将该层蚀刻以形成一次性间隔件。器件结构可以包括衬底和栅极结构，其中一次性间隔物形成在其侧壁处。此外，器件结构可以包括其上形成有氧化掩模的衬底，其中一次性间隔物相对于氧化掩模的侧壁形成。此外，该方法包括通过氧化间隔物以除去一次性间隔物以形成挥发性GexSiyO。任何未挥发的GexSiyO可以用水除去。此外，可以使用包括氢氧化铵的清洁溶液进行去除步骤。

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