专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5901302A Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions 失效
标题翻译：超标量微处理器具有对称的，固定的发布位置，每个配置成执行特定的指令子集
公开(公告)号：US5901302A
公开(公告)日：1999-05-04
申请号：US690384
申请日：1996-07-26
申请人： David B. Witt , Thang M. Tran
发明人： David B. Witt , Thang M. Tran
IPC分类号： G06F9/38 , G06F9/46 , G06F12/12
CPC分类号： G06F9/52 , G06F12/126 , G06F9/30036 , G06F9/382 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A microprocessor employing a reorder buffer is configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. In one embodiment, the reorder buffer allocates a line of storage sufficient to store instruction results corresponding to a maximum number of concurrently dispatchable instructions regardless of the number actually dispatched. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases.
摘要翻译：采用重排序缓冲器的微处理器配置有固定的对称发布位置。问题位置的对称性质可能会增加由微处理器同时调度和执行的指令的平均数量。在一个实施例中，重新排序缓冲器分配足够的存储线，以便存储对应于最大数量的可同时分发的指令的指令结果，而不管实际发送的数目如何。随着并发调度指令的平均数量的增加，行中未使用位置的平均数量减少。

72. 发明授权

US5898851A Method and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operations 失效
标题翻译：用于扫描多个RISC操作的五位预解码可变长度指令的方法和装置
公开(公告)号：US5898851A
公开(公告)日：1999-04-27
申请号：US873115
申请日：1997-06-11
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/345 , G06F9/318 , G06F9/40
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and two ROP bits. The ROP bits indicate a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified. Accordingly, relatively fast multiplexing may be attained, and high performance may be accommodated.
摘要翻译：提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。预解码单元被配置为为每个指令字节生成多个预解码位。与每个指令字节相关联的多个预解码位包括结束位和两个ROP位。 ROP位指示实现该指令所需的微指令数。多个预解码比特统称为预解码标签。指令对齐单元然后使用预解码标签来识别微指令。指令对准单元将微指令同时分配到在超标量微处理器内形成固定发行位置的多个解码单元。由于指令对准单元识别微指令，简化了从指令对准单元到解码器的指令的复用。因此，可以实现相对快速的复用，并且可以适应高性能。

73. 发明授权

US5887152A Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions 失效
标题翻译：加载/存储单元具有多个最早的未完成指令指针，用于完成存储和加载/存储错误指令
公开(公告)号：US5887152A
公开(公告)日：1999-03-23
申请号：US420737
申请日：1995-04-12
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3855 , G06F9/3857
摘要： A superscalar microprocessor is provided having a load/store unit which receives a pair of pointers identifying the oldest outstanding instructions which are not in condition for retirement. The load/store unit compares these pointers with the reorder buffer tags of load instructions that miss the data cache and store instructions. A match must be found before the associated instruction accesses the data cache and the main memory system. The pointer-compare mechanism provides an ordering mechanism for load instructions that miss the data cache and store instructions.
摘要翻译：提供了一种超标量微处理器，其具有负载/存储单元，该单元接收一对指示符，用于识别不符合退休条件的最早的未完成指令。加载/存储单元将这些指针与错过数据高速缓存和存储指令的加载指令的重新排序缓冲区标记进行比较。必须在关联指令访问数据高速缓存和主存储器系统之前找到匹配项。指针比较机制为缺少数据高速缓存和存储指令的加载指令提供了排序机制。

74. 发明授权

US5878244A Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received 失效
标题翻译：重新排序缓冲器被配置为分配能够存储对应于最大数量的并发可接收指令的结果的存储器，而不管接收的指令数量
公开(公告)号：US5878244A
公开(公告)日：1999-03-02
申请号：US690385
申请日：1996-07-26
申请人： David B. Witt , Thang M. Tran
发明人： David B. Witt , Thang M. Tran
IPC分类号： G06F9/38 , G06F9/46 , G06F12/12
CPC分类号： G06F9/3836 , G06F12/126 , G06F9/30036 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/52
摘要： A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instructions results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. The line of storage remains allocated until each instruction within the line is ready to retire, and then the line is deallocated as the one or more instructions are concurrently retired.
摘要翻译：重排序缓冲器被配置成多行存储器，其中一行存储器包括足够的存储器，用于关于预定的最大数量的可同时发送的指令的指令结果。只要调度一个或多个指令，就分配一行存储空间。存储线保持分配，直到行内的每条指令准备退出，然后该线路被释放，因为一个或多个指令同时退出。

75. 发明授权

US5872943A Apparatus for aligning instructions using predecoded shift amounts 失效
标题翻译：用于使用预解码移位量对准指令的装置
公开(公告)号：US5872943A
公开(公告)日：1999-02-16
申请号：US690382
申请日：1996-07-26
申请人： James K. Pickett , Thang M. Tran
发明人： James K. Pickett , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38 , G06F9/312
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3822
摘要： A predecode unit within a microprocessor predecodes a cache line of instruction bytes for storage within the instruction cache of the microprocessor. The predecode unit produces multiple shift amounts, each of which identify the beginning of a particular instruction within the instruction cache line. The shift amounts are stored in the instruction cache with the instruction bytes, and are conveyed when the instruction bytes are fetched for execution by the microprocessor. An instruction alignment unit decodes the shift amounts to locate instructions within the fetched instruction bytes. Each shift amount directly identifies a corresponding instruction for dispatch, and therefore decoding the shift amount directly results in controls for shifting the instruction bytes such that the identified instruction is conveyed to a corresponding issue position. The number of shift amounts stored may be equal to the number of issue positions within the microprocessor. The instruction alignment unit scans the start and end byte predecode data (which is also provided by the predecode unit and stored in the instruction cache) to detect any additional instructions within the cache line (e.g. instructions not identified by the shift amounts). Additional shift amounts are generated and used by the instruction alignment unit to dispatch instructions during subsequent clock cycles.
摘要翻译：微处理器中的预解码单元预先对指令字节的高速缓存行进行存储，以存储在微处理器的指令高速缓存内。预解码单元产生多个移位量，每个移位量标识指令高速缓存行内特定指令的开始。移位量存储在具有指令字节的指令高速缓存中，并且当指令字节被提取以由微处理器执行时被传送。指令对准单元对移位量进行解码，以定位取出的指令字节内的指令。每个移位量直接识别用于调度的相应指令，因此解码移位量直接导致用于移位指令字节的控制，使得所识别的指令被传送到相应的发行位置。存储的移位量的数量可以等于微处理器内的发放位置的数目。指令对准单元扫描开始和结束字节预解码数据（其也由预解码单元提供并存储在指令高速缓存中）以检测高速缓存行内的任何附加指令（例如，未被移位量标识的指令）。附加移位量由指令对准单元产生并用于在随后的时钟周期期间调度指令。

76. 发明授权

US5859992A Instruction alignment using a dispatch list and a latch list 失效
标题翻译：指令对齐使用调度列表和锁存列表
公开(公告)号：US5859992A
公开(公告)日：1999-01-12
申请号：US815566
申请日：1997-03-12
申请人： Thang M. Tran , Rammohan Narayan , Jagadish V. Nayak
发明人： Thang M. Tran , Rammohan Narayan , Jagadish V. Nayak
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： An instruction alignment unit includes a byte queue configured to store instruction blocks. Each instruction block includes a fixed number of instruction bytes and identifies up to a maximum number of instructions within the fixed number of instruction bytes. Additionally, the instruction alignment unit is configured to form a pair of instruction lists: a dispatch list and a latch list. The dispatch list includes instruction locators corresponding to instructions within the instruction blocks stored in the byte queue. Additionally, the first three instructions from instructions blocks being received from the instruction cache during a particular clock cycle are appended to the dispatch list. The dispatch list is used to select instructions from the byte queue for dispatch to the decode units. The latch list is used for receiving instruction locators for the remaining instructions from the instruction blocks received from the instruction cache during the particular clock cycle. Furthermore, the latch list receives instruction locators from the dispatch list which correspond to instructions not selected for dispatch to the decode units. The latch list is stored until a succeeding clock cycle, in which the stored program-ordered list is used as a basis for forming the dispatch list during that succeeding clock cycle. The instruction identification information and instruction bytes corresponding to the instruction can be located by selecting the instructions corresponding to the instruction locators at the front of the dispatch list.
摘要翻译：指令对准单元包括被配置为存储指令块的字节队列。每个指令块包括固定数量的指令字节，并且在固定数目的指令字节内识别最多指令数。此外，指令对准单元被配置为形成一对指令列表：调度列表和锁存列表。调度列表包括对应于存储在字节队列中的指令块内的指令的指令定位符。此外，在特定时钟周期期间从指令高速缓存接收到来自指令块的前三个指令被附加到调度列表。调度列表用于从字节队列中选择用于调度到解码单元的指令。锁存列表用于从特定时钟周期内从指令高速缓存接收到的指令块接收剩余指令的指令定位器。此外，锁存列表从调度列表接收与未被选择用于发送到解码单元的指令对应的指令定位器。存储锁存列表直到下一个时钟周期，其中存储的程序排序列表用作在该后续时钟周期期间形成分派列表的基础。可以通过选择与调度列表前面的指令定位符相对应的指令来定位与该指令相对应的指令识别信息和指令字节。

77. 发明授权

US5848433A Way prediction unit and a method for operating the same 失效
标题翻译：方式预测单元及其操作方法
公开(公告)号：US5848433A
公开(公告)日：1998-12-08
申请号：US838680
申请日：1997-04-09
申请人： Thang M. Tran , James K. Pickett
发明人： Thang M. Tran , James K. Pickett
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F9/3806 , G06F12/0864 , G06F9/3832 , G06F2212/6082
摘要： A way prediction unit for a superscalar microprocessor is provided which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The way prediction unit is intended for high frequency microprocessors in which associative caches tend to be clock cycle limiting, causing the instruction fetch mechanism to require more than one clock cycle between fetch requests. Therefore, an instruction fetch can be made every clock cycle using the predicted fetch address until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.
摘要翻译：提供了一种用于超标量微处理器的方式预测单元，其预测下一个提取地址以及当前提取地址所在的指令高速缓存的方式，同时从指令高速缓存读取与当前提取相关联的指令。预测单元用于高频微处理器的方式，其中关联高速缓存趋向于是时钟周期限制，导致指令获取机制在提取请求之间需要多于一个时钟周期。因此，可以使用预测的提取地址进行每个时钟周期的指令提取，直到预测到不正确的下一个提取地址或错误的方式。来自预测方式的指令被提供给超标量微处理器每个时钟周期的指令处理流水线。

78. 发明授权

US5835968A Apparatus for providing memory and register operands concurrently to functional units 失效
标题翻译：用于向功能单元同时提供存储器和寄存器操作数的装置
公开(公告)号：US5835968A
公开(公告)日：1998-11-10
申请号：US633302
申请日：1996-04-17
申请人： Rupaka Mahalingaiah , Thang M. Tran
发明人： Rupaka Mahalingaiah , Thang M. Tran
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0875 , G06F9/3826 , G06F9/3832
摘要： An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.
摘要翻译：提供了包括地址生成单元，相应的保留站和推测寄存器文件的装置。解码单元在对相关指令进行解码的同时向对应的保留站提供存储器操作信息。推测寄存器文件存储与先前解码的指令相对应的推测寄存器值。在执行先前解码的指令之前生成推测寄存器值。如果包含在指令的地址操作数中的寄存器操作数存储在推测寄存器文件中，则存储器操作可以通过相应的保留站传递给地址生成单元。地址生成单元从地址操作数生成数据地址，并访问数据高速缓存，同时从寄存器文件和重排序缓冲器请求与指令对应的寄存器操作数。

79. 发明授权

US5822558A Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器内预编码可变字节长度指令的方法和装置
公开(公告)号：US5822558A
公开(公告)日：1998-10-13
申请号：US790394
申请日：1997-01-29
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30152 , G06F9/30167 , G06F9/3806 , G06F9/3816 , G06F9/382 , G06F9/3832
摘要： A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. With the information conveyed by the functional bits, the decode units can detect the exact locations of the opcode, displacement, immediate, register, and scale-index bytes. Accordingly, no serial scan by the decode units through the instruction bytes is needed. In addition, the functional bits allow the decode units to calculate linear addresses (via adder circuits) expeditiously for use by other subunits within the superscalar microprocessor. Accordingly, relatively fast decoding may be attained, and high performance may be accommodated.
摘要翻译：提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。预解码单元被配置为为每个指令字节生成多个预解码位。与每个指令字节相关联的多个预解码位被统称为预解码标签。指令对准单元然后使用预解码标签将可变字节长度指令同时分配到在超标量微处理器内形成固定发布位置的多个解码单元。通过功能位传送的信息，解码单元可以检测操作码，位移，立即数，寄存器和缩放索引字节的确切位置。因此，不需要通过指令字节的解码单元的串行扫描。此外，功能位允许解码单元计算线性地址（通过加法器电路），以便迅速地由超标量微处理器内的其他子单元使用。因此，可以获得相对快速的解码，并且可以适应高性能。

80. 发明授权

US5819059A Predecode unit adapted for variable byte-length instruction set processors and method of operating the same 失效
标题翻译：适用于可变字节长度指令集处理器的预编码单元及其操作方法
公开(公告)号：US5819059A
公开(公告)日：1998-10-06
申请号：US421663
申请日：1995-04-12
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3885
摘要： A superscalar microprocesor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. By utilizing the predecode information from the predecode unit, the instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accommodating very high frequencies of operation. Instruction alignment to decode units may further be accomplished with relatively few pipeline stages. Finally, since the predecode unit is configured such that the meaning of the functional bit of a particular predecode tag is dependent upon the status of the start bit, a relatively large amount of predecode information may be conveyed with a relatively small number of predecode bits. This thereby allows a reduction in the size of the instruction cache without compromising performance.
摘要翻译：提供了一种超标量微处理器，其包括适于预编码可变字节长度指令的预解码单元。预解码单元在指令存储之前对指令进行预解码。在一个系统中，预解码单元被配置为为每个指令字节生成多个预解码位。与每个指令字节相关联的多个预解码位被统称为预解码标签。指令对准单元然后使用预解码标签将可变字节长度指令同时分配到在超标量微处理器内形成固定发布位置的多个解码单元。通过利用来自预解码单元的预解码信息，指令对准单元可以用相对较少数量的级联的逻辑门来实现，从而适应非常高的操作频率。解码单元的指令对准可以在相对较少的流水线阶段进一步完成。最后，由于预解码单元被配置为使得特定预解码标签的功能位的含义取决于起始位的状态，所以相对大量的预解码信息可以用相对较少数量的预先解码位来传送。这样就可以减小指令高速缓存的大小，而不会影响性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式