专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US06180461B2 Double sidewall short channel split gate flash memory 有权
标题翻译：双侧壁短通道分闸门闪存
公开(公告)号：US06180461B2
公开(公告)日：2001-01-30
申请号：US09128585
申请日：1998-08-03
申请人： Seiki Ogura
发明人： Seiki Ogura
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.
摘要翻译：提供了具有从通道到浮动栅极的电子注入效率的电可编程只读存储器件。该存储单元包括在源极和漏极区之间的控制栅极和浮置栅极。浮动栅极下的区域具有非常小的增强模式通道和N区域。因此，该通道完全耗尽程序漏极电压。增强模式通道区域由侧壁间隔技术精确地限定。此外，N漏极区域由侧壁多晶硅栅极和第一间隔物的差异精确地限定。

72. 发明授权

US6157058A Low voltage EEPROM/NVRAM transistors and making method 失效
公开(公告)号：US6157058A
公开(公告)日：2000-12-05
申请号：US111720
申请日：1998-07-08
申请人： Seiki Ogura
发明人： Seiki Ogura
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11553 , H01L27/11556 , H01L29/42324 , H01L29/7885
摘要： A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.

73. 发明授权

US6121655A Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit 失效
标题翻译：非易失性半导体存储器件及其制造方法和半导体集成电路
公开(公告)号：US6121655A
公开(公告)日：2000-09-19
申请号：US848
申请日：1997-12-30
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/7885
摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.
摘要翻译：本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层，形成在远离通道区域的区域中。由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

74. 发明授权

US6038169A Read reference scheme for flash memory 失效
标题翻译：读取闪存的参考方案
公开(公告)号：US6038169A
公开(公告)日：2000-03-14
申请号：US270596
申请日：1999-03-18
申请人： Seiki Ogura , Tomoko Ogura
发明人： Seiki Ogura , Tomoko Ogura
IPC分类号： G11C11/56 , G11C16/28 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C16/28 , G11C2211/5634
摘要： In this invention a reference circuit is disclosed that produces a reference current to be used in determining the value of data in a flash memory cell. The memory cell current is compared to the reference current in a sense amplifier. A reference circuit that generates the reference current is connect to each bit line of the flash memory and uses bit lines that are not activated when a particular cell is being read to connect the reference current to the sense amplifiers. The use of a reference current allows multi-bit cells to be read by using a variation on the reference circuit that has a plurality of reference transistors creating a plurality of reference currents.. Verification of the programmed and erase states of a flash memory cell can be determined using different values of the reference current that are easily set in the reference circuit by changing a reference voltage.
摘要翻译：在本发明中，公开了一种参考电路，其产生用于确定闪存单元中的数据值的参考电流。将存储单元电流与读出放大器中的参考电流进行比较。产生参考电流的参考电路连接到闪存的每个位线，并且使用当读取特定单元以将参考电流连接到读出放大器时未被激活的位线。使用参考电流允许通过使用具有多个参考晶体管的参考电路上的变化来读取多位单元，该参考电路产生多个参考电流。闪存单元的编程和擦除状态的验证可以可以通过改变参考电压来容易地在参考电路中设置的参考电流的不同值来确定。

75. 发明授权

US5910912A Flash EEPROM with dual-sidewall gate 失效
标题翻译：具有双侧壁门的闪存EEPROM
公开(公告)号：US5910912A
公开(公告)日：1999-06-08
申请号：US968736
申请日：1992-10-30
申请人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
发明人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/2815 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.
摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

76. 发明授权

US5541130A Process for making and programming a flash memory array 失效
标题翻译：制作和编程闪存阵列的过程
公开(公告)号：US5541130A
公开(公告)日：1996-07-30
申请号：US477791
申请日：1995-06-07
申请人： Seiki Ogura , Nivo Rovedo , Robert C. Wong
发明人： Seiki Ogura , Nivo Rovedo , Robert C. Wong
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/972
摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.
摘要翻译：一种用于制造高密度存储器阵列的方法。将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。每个扩散轨定义相应的位线。每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

77. 发明授权

US5466625A Method of making a high-density DRAM structure on SOI 失效
标题翻译：在SOI上制造高密度DRAM结构的方法
公开(公告)号：US5466625A
公开(公告)日：1995-11-14
申请号：US346207
申请日：1994-11-22
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10829 , H01L27/10823
摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.
摘要翻译：具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

78. 发明授权

US5283456A Vertical gate transistor with low temperature epitaxial channel 失效
标题翻译：具有低温外延通道的垂直栅极晶体管
公开(公告)号：US5283456A
公开(公告)日：1994-02-01
申请号：US900038
申请日：1992-06-17
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
IPC分类号： H01L21/265 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/01 , H01L29/76
CPC分类号： H01L29/78642 , H01L27/1203
摘要： A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.
摘要翻译：具有垂直栅极和夹在源极和漏极层之间的非常薄的沟道的场效应晶体管（FET）。在本发明的一个优选实施例中，FET在硅绝缘体（SOI）衬底上形成，硅层用作第一层（例如，源层）。使用低温外延（LTE）工艺来形成非常薄的（例如0.1（m））沟道，并且化学气相沉积的多晶硅层形成顶层（例如，漏层）。通过三层蚀刻开口到绝缘体衬底，并且其壁被氧化，形成栅极氧化物。沉积多晶硅以填充开口并形成垂直浇口。

79. 发明授权

US5155572A Vertical isolated-collector PNP transistor structure 失效
标题翻译：垂直隔离集电极PNP晶体管结构
公开(公告)号：US5155572A
公开(公告)日：1992-10-13
申请号：US680490
申请日：1991-04-04
申请人： Dominique Bonneau , Myriam Combes , Anthony J. Dally , Pierre Mollier , Seiki Ogura , Pascal Tannhof
发明人： Dominique Bonneau , Myriam Combes , Anthony J. Dally , Pierre Mollier , Seiki Ogura , Pascal Tannhof
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/73 , H01L29/732 , H01L29/74
CPC分类号： H01L29/74 , H01L29/0821
摘要： A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).
摘要翻译：垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用，（48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

80. 依法登记的发明

USH986H Field effect-transistor with asymmetrical structure 失效
公开(公告)号：USH986H
公开(公告)日：1991-11-05
申请号：US363747
申请日：1989-06-09
申请人： Christopher F. Codella , Nivo Rovedo , Seiki Ogura
发明人： Christopher F. Codella , Nivo Rovedo , Seiki Ogura
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28132 , H01L29/1033 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式