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71. 发明专利

IL187038D0 SECURE DATA PROCESSING FOR UNALIGNED DATA 未知
公开(公告)号：IL187038D0
公开(公告)日：2008-02-09
申请号：IL18703807
申请日：2007-10-30
申请人： SANDISK IL LTD
IPC分类号： G06F21/60
摘要： A method for data cryptography includes accepting input data, which contains a section that is to undergo a cryptographic operation and starts at an offset with respect to a beginning of the input data, by a Direct Memory Access (DMA) module. The input data is aligned by the DMA module to cancel out the offset. The aligned input data is read out of the DMA module, and the cryptographic operation is performed on the section.

72. 发明专利

IL148834A REMOVABLE, ACTIVE, PERSONAL STORAGE DEVICE, SYSTEM AND METHOD 未知
公开(公告)号：IL148834A
公开(公告)日：2007-03-08
申请号：IL14883402
申请日：2002-03-21
申请人： SANDISK IL LTD , RAZ DAN , MORAN DOV , ELAZAR GIDI , HARKABI DAN
发明人： RAZ DAN , MORAN DOV , ELAZAR GIDI , HARKABI DAN
IPC分类号： G06F20060101

73. 发明专利

IL158578A ARCHITECTURE FOR A UNIVERSAL SERIAL BUS-BASED PC FLASH DISK 未知
公开(公告)号：IL158578A
公开(公告)日：2006-12-10
申请号：IL15857803
申请日：2003-10-23
申请人： MORAN DOV , BAN AMIR , SANDISK IL LTD , OGDAN ORON
发明人： MORAN DOV , BAN AMIR , OGDAN ORON
IPC分类号： G06F13/10 , G06F3/06 , G06F3/08 , G06F13/36 , G06F13/38 , G11C7/10
摘要： A storage unit made of a flash array (58) and a Universal Serial Bus (USB) controller (56) is implemented to be compatible with the USB specification. The unit (46) includes memory modules (58) which can accept write commands and read commands from a host (44), and are erasable and non-volatile, referred to as flash modules (58). The USB/flash controller (56) is configured to provide USB functionality and compatibility along with common flash operations such as programming, reading, and erasing the flash modules (58).

74. 发明专利

IL151293A METHOD FOR FAST WAKE-UP OF A FLASH MEMORY SYSTEM 未知
公开(公告)号：IL151293A
公开(公告)日：2006-10-31
申请号：IL15129302
申请日：2002-02-03
申请人： SANDISK IL LTD , LASSER MENAHEM
发明人： LASSER MENAHEM
IPC分类号： G06F12/16 , G06F20060101 , G06F3/06 , G06F12/00
摘要： A system and method for enabling a fast wake-up of a flash memory system, without compromising the integrity of the flash data structures and without risking loss of data. This is achieved by storing translation tables in the flash, but adding some means for the software to invalidate them in a way that is detectable whenever reading them. Possible implementations include adding a checksum value that makes the sum of all entries equal some fixed known value, or adding a validity flag to the stored tables, enabling the tables to be invalidated at will. In addition, one should ask the application software to call a specific function in the translation layer before shutting the system down. The present invention enables fast wake-ups when the application software made an orderly exit and made us store the tables. In the case an orderly exit was not made, the present invention commands a regular wake-up procedure, thereby ensuring data intengrity.

75. 发明专利

CA2601469A1 LOADING INTERNAL APPLICATIONS ON A SMARTCARD 未知
公开(公告)号：CA2601469A1
公开(公告)日：2006-09-28
申请号：CA2601469
申请日：2006-03-19
申请人： SANDISK IL LTD
发明人： AGAMI MISHAEL , DARIEL DANI
IPC分类号： G06K19/06
摘要： Portable smartcard devices, methods of executing program code using smartcard devices, and computer readable storage media including instructions for smartcard devices are provided. According to some embodiments, the presently disclosed smartcard device includes an interface for presenting smartcard functionality to a host system and for receiving a program execution command from the host system, non-volatile memory, executable memory, a copying mechanism such as an internal copying mechanism for copying program code from the non-volatile memory to the executable memory, and a program execution mechanism for executing the program code. Appropriate interfaces include but are not limited to ISO 7816 compatible interfaces, USB interfaces, and MMC interfaces. In some embodiments, the smartcard functionality includes SIM functionality and/or USIM functionality. Optionally, execution of the program code commences when only a portion of the copied executable code resides in the executable memory. A method of delivering pre-loaded protected executable code to smartcard users is disclosed.

76. 发明专利

BR0006063B1 未知
公开(公告)号：BR0006063B1
公开(公告)日：2014-07-22
申请号：BR0006063
申请日：2000-03-20
申请人： SANDISK IL LTD
发明人： BAN AMIR , MORAN DOV , OGDAN ORON
IPC分类号： G06F13/10 , G06F13/36 , G06F3/06 , G06F3/08 , G06F13/38 , G11C7/10
摘要： A storage unit made of a flash array (58) and a Universal Serial Bus (USB) controller (56) is implemented to be compatible with the USB specification. The unit (46) includes memory modules (58) which can accept write commands and read commands from a host (44), and are erasable and non-volatile, referred to as flash modules (58). The USB/flash controller (56) is configured to provide USB functionality and compatibility along with common flash operations such as programming, reading, and erasing the flash modules (58).

77. 发明专利

SG186496A1 ARCHITECTURE FOR A UNIVERSAL SERIAL BUS-BASED PC FLASH DISK 未知
公开(公告)号：SG186496A1
公开(公告)日：2013-01-30
申请号：SG2010097178
申请日：2000-03-20
申请人： SANDISK IL LTD
发明人： AMIR BAN , DOV MORAN , ORON OGDAN
IPC分类号： G06F13/10 , G06F3/06 , G06F3/08 , G06F13/36 , G06F13/38 , G11C7/10
摘要： A storage unit made of a flash array (58) and a Universal Serial Bus (USB) controller (56) is implemented to be compatible with the USB specification. The unit (46) includes memory modules (58) which can accept write commands and read commands from a host (44), and are erasable and non-volatile, referred to as flash modules (58). The USB/flash controller(56) is configured to provide USB functionality and compatibility along with common flash operations such as programming, reading, and erasing the flash modules (58).Figure 5

78. 发明专利

AT538475T 未知
公开(公告)号：AT538475T
公开(公告)日：2012-01-15
申请号：AT09766316
申请日：2009-06-15
申请人： SANDISK IL LTD
发明人： LASSER MENAHEM
IPC分类号： G11C16/10
摘要： To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the word lines has a higher logical page address than any page that is written to a subsequently written word line, regardless of the sequence in which the pages are received for writing. Alternatively, the pages are written to the word lines so that for every pair of written word lines, the word line of the pair that is earlier in the writing order has written thereto a page having a higher logical page address than at least one page written to the other word line of the pair.

79. 发明专利

AT534072T 未知
公开(公告)号：AT534072T
公开(公告)日：2011-12-15
申请号：AT09718069
申请日：2009-02-25
申请人： SANDISK IL LTD
发明人： DROR ITAI , MINZ LEONID , DOLGUNOV BORIS , KOUN MICHAEL
IPC分类号： G06F7/58
摘要： A system for random number generation includes a digital oscillator circuit, which has a set of available configurations and is operative to generate a random number sequence in accordance with a current configuration selected from the set. The system further includes a randomization circuit, which is operative to produce a pseudo-random stream of values corresponding to the available configurations of the digital oscillator circuit, and to control the digital oscillator circuit to alternate among the available configurations in accordance with the pseudo-random stream of values.

80. 发明专利

AT506649T 未知
公开(公告)号：AT506649T
公开(公告)日：2011-05-15
申请号：AT08807915
申请日：2008-10-07
申请人： SANDISK IL LTD
发明人： EREZ ERAN
IPC分类号： G06F11/10
摘要： A computer system for correction of errors in a memory array includes an error correction algorithm and a memory. The error correction algorithm is capable of correcting errors up to a first bit error rate in a correctable group of memory cells having a standard size. The memory is operative to store a first set of ECC bits having information corresponding to a first group of memory cells having a first size larger than the standard size, and to store a second set of ECC bits having information corresponding to a second group of memory cells having a second size smaller than said first size and being a portion of said first group. The error correction algorithm is operative to correct errors in the second group based on the second set of ECC bits if a failure occurs in correction of the first group based on the first set of ECC bits.

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