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71. 发明申请

US20070266347A1 Method of automatic synthesis of sequential quantum Boolean circuits 失效
标题翻译：自动合成顺序量子布尔电路的方法
公开(公告)号：US20070266347A1
公开(公告)日：2007-11-15
申请号：US11430987
申请日：2006-05-10
申请人： Li-Kai Chang , Fu-Chiung Cheng
发明人： Li-Kai Chang , Fu-Chiung Cheng
IPC分类号： G06F17/50
CPC分类号： B82Y10/00 , G06N99/002
摘要： A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an integer; (B) determining whether the state graph is reversible; (C) encoding the M state nodes by using a unique state encoding when step (B) decides that the state graph is reversible, and producing a unique state coding reversible state graph; (D) transferring the unique state coding reversible state graph (USCRSG) into a corresponding self-timed transformation graph; (E) performing a state decomposition on the self-timed transformation graph and producing a decomposed self-timed transformation graph; and (F) constructing a quantum Boolean circuit of the decomposed self-timed transformation graph.
摘要翻译：一种自动合成顺序量子布尔电路的方法，用于将自定时电路传送到顺序量子布尔电路中，并合成顺序量子布尔电路，其包括以下步骤：（A）将自定时电路传送到状态图具有M个状态节点，其中M是整数; （B）确定状态图是否可逆; （C）当步骤（B）判定状态图是可逆的时，通过使用唯一状态编码对M个状态节点进行编码，并产生唯一的状态编码可逆状态图; （D）将唯一状态编码可逆状态图（USCRSG）转移到相应的自定时变换图中; （E）对自适应变换图进行状态分解并产生分解的自时变换图; 和（F）构建分解的自定时变换图的量子布尔电路。

72. 发明申请

US20070157132A1 Process of automatically translating a high level programming language into a hardware description language 审中-公开
标题翻译：自动将高级编程语言翻译成硬件描述语言的过程
公开(公告)号：US20070157132A1
公开(公告)日：2007-07-05
申请号：US11472365
申请日：2006-06-22
申请人： Fu-Chiung Cheng , Jian-Yi Chen , Kuan-Yu Yan , Shin-Hway Yu , Kuan-Yu Chen , Chieh-Ju Wang , Shu-Ming Chang , Ping-Yun Wang , Li-Kai Chang , Chin-Tai Chou , Chi-Huam Shieh , Ming-Shiou Chiang , Nian-Zhi Huang , Hung-Chi Wu
发明人： Fu-Chiung Cheng , Jian-Yi Chen , Kuan-Yu Yan , Shin-Hway Yu , Kuan-Yu Chen , Chieh-Ju Wang , Shu-Ming Chang , Ping-Yun Wang , Li-Kai Chang , Chin-Tai Chou , Chi-Huam Shieh , Ming-Shiou Chiang , Nian-Zhi Huang , Hung-Chi Wu
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level programming language into an extended activity diagram (EAD). The second stage translates the EAD into a hardware component graph (HCG). The third stage generates the respective signal connections of HDL components according to all edges of the HCG, and outputs an HDL entity and architecture to a file in a string form, thereby completing the entire translation.
摘要翻译：自动将高级编程语言翻译成硬件描述语言（HDL）的过程，其可以使用三级转换机制来生成与由高级编程语言描述的功能相对应的HDL代码。第一阶段将由高级编程语言编码的源代码转换为扩展活动图（EAD）。第二阶段将EAD转换为硬件组件图（HCG）。第三阶段根据HCG的所有边缘生成HDL组件的相应信号连接，并将HDL实体和体系结构输出到字符串形式的文件，从而完成整个翻译。

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