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71. 发明申请

US20080138931A1 Method for Making a Self-Converged Void and Bottom Electrode for Memoery Cell 有权
标题翻译：制备用于记忆单元的自会聚空隙和底电极的方法
公开(公告)号：US20080138931A1
公开(公告)日：2008-06-12
申请号：US11567326
申请日：2006-12-06
申请人： Hsiang Lan Lung
发明人： Hsiang Lan Lung
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer.
摘要翻译：形成包括导电元件的基层。在基层上形成包括第三下平面化停止层，第二层和第一上层的上层。键孔通过上层形成，露出基层中导电元件的表面。第一层具有延伸到开口中的突出部分，使得第一层中的开口比第二层中的开口短。电介质材料沉积到锁眼孔中以在沉积的介电材料内形成自会聚空隙。在一些示例中，键孔形成步骤包括增加第一层的体积，而在其他示例中，键孔形成步骤包括蚀刻第二层。

72. 发明申请

US20070298535A1 Memory Cell With Memory Material Insulation and Manufacturing Method 有权
标题翻译：具有记忆材料绝缘和制造方法的记忆单元
公开(公告)号：US20070298535A1
公开(公告)日：2007-12-27
申请号：US11426771
申请日：2006-06-27
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A memory cell, the memory cell includes first and second electrodes and a memory material element electrically coupling the first and second electrodes. The memory material element comprises a first memory material, such as GST, the first memory material having an electrical property that can be changed by the application of energy. A thermal insulating layer surrounds the memory material element. The thermal insulating layer comprises a second memory material. A dielectric layer separates the thermal insulating material from the memory material element. A method for making a thermally insulated memory cell device is also disclosed.
摘要翻译：存储单元，存储单元包括第一和第二电极以及电耦合第一和第二电极的存储材料元件。存储材料元件包括诸如GST的第一存储器材料，第一存储器材料具有能够通过施加能量而改变的电特性。绝热层围绕着记忆材料元件。绝热层包括第二记忆材料。介电层将绝热材料与记忆材料元件分开。还公开了一种制造绝热存储单元器件的方法。

73. 发明申请

US20070176261A1 Vertical Side Wall Active Pin Structures in a Phase Change Memory and Manufacturing Methods 有权
标题翻译：相变存储器中的垂直侧壁有源引脚结构和制造方法
公开(公告)号：US20070176261A1
公开(公告)日：2007-08-02
申请号：US11381397
申请日：2006-05-03
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： A programmable resistor memory, such as a phase change memory, with a memory element comprising narrow vertical side wall active pins is described. The side wall active pins comprise a programmable resistive material, such as a phase change material. In a first aspect of the invention, a method of forming a memory cell is described which comprises forming a stack comprising a first electrode having a principal surface with a perimeter, an insulating layer overlying a portion of the principal surface of the first electrode, and a second electrode vertically separated from the first electrode and overlying the insulating layer. Side walls on the insulating layer and on the second electrode are positioned over the principle surface of the first electrode with a lateral offset from the perimeter of the first electrode.
摘要翻译：描述了一种可编程电阻存储器，例如相变存储器，具有包括窄垂直侧壁有源引脚的存储元件。侧壁有源引脚包括可编程电阻材料，例如相变材料。在本发明的第一方面中，描述了一种形成存储单元的方法，该方法包括：形成堆叠，该堆叠包括具有主表面的周边的第一电极，覆盖在第一电极的主表面的一部分上的绝缘层;以及与第一电极垂直分离并覆盖绝缘层的第二电极。绝缘层和第二电极上的侧壁位于第一电极的主表面上方，其侧面偏离第一电极的周边。

74. 发明授权

US07251167B2 Method for programming multi-level nitride read-only memory cells 有权
标题翻译：多级氮化物只读存储单元的编程方法
公开(公告)号：US07251167B2
公开(公告)日：2007-07-31
申请号：US11026947
申请日：2004-12-29
申请人： Hsiang-Lan Lung , Chao-I Wu
发明人： Hsiang-Lan Lung , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： H01L29/7923
摘要： A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride read-only memory cell are programmed in a time order according to their descending Vt values. For a nitride read-only memory cell that, in an erased state, exhibits a high Vt value, a data region that is to be programmed to a lowest Vt value is programmed first with remaining data regions programmed in a time order according to their ascending Vt values.
摘要翻译：描述了在氮化物只读存储器单元中编程数据区域的方法。在擦除状态下，氮化物只读存储器单元呈现低V值。首先编程要编程到最高V SUB值的数据区。氮化物只读存储器单元中的剩余数据区域按照其下降的V t值的时间顺序被编程。对于在擦除状态下呈现高V V值的氮化物只读存储器单元，要编程到最低V OUT值的数据区域首先编程其余数据区域按照时间顺序按照它们的升序值编程。

75. 发明申请

US20070158645A1 Self-align planerized bottom electrode phase change memory and manufacturing method 有权
标题翻译：自对准平面化底电极相变记忆及制造方法
公开(公告)号：US20070158645A1
公开(公告)日：2007-07-12
申请号：US11351296
申请日：2006-02-09
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/08
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.
摘要翻译：描述了一种用于在相变随机存取存储器PCRAM器件中自对准底部电极的方法，其中顶部电极用作底部电极的自对准蚀刻的掩模。底部电极具有通过化学机械抛光而平坦化的顶表面。顶部电极还具有通过化学机械抛光而平坦化的顶表面。在衬底上形成TiN的底部电极层，并且在随后的工艺步骤中形成通孔之前。第一电介质层形成在底电极层的上方，第二电介质层形成在第一电介质层上。通孔形成在延伸穿过第一和第二电介质层的选定部分。

76. 发明申请

US20070131922A1 Thin Film Fuse Phase Change Cell with Thermal Isolation Pad and Manufacturing Method 有权
标题翻译：薄膜保险丝相变电池与隔热垫和制造方法
公开(公告)号：US20070131922A1
公开(公告)日：2007-06-14
申请号：US11425183
申请日：2006-06-20
申请人： Hsiang Lan Lung
发明人： Hsiang Lan Lung
IPC分类号： H01L29/06
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/1293 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode extends outwardly from the top sides of the first and second electrodes defining a wall of insulating material having top side. A bridge of memory material crosses the insulating member over the top of the wall, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises an active layer of memory material on the top side of the wall, having at least two solid phases and a layer of thermal insulating material overlying the memory material having thermal conductivity less than a thermal conductivity of the first and second electrodes.
摘要翻译：一种存储器件，包括具有顶侧的第一电极，具有顶侧的第二电极和位于第一电极和第二电极之间的绝缘构件。绝缘构件具有在第一电极的顶侧附近的第一和第二电极之间的厚度，并且第二电极的顶侧从第一和第二电极的顶侧向外延伸，限定具有顶侧的绝缘材料的壁。记忆材料桥跨越顶部的绝缘构件，并且在绝缘构件之间限定第一和第二电极之间的电极间路径。提供这样的存储单元阵列。该桥包括在壁的顶侧上的存储材料的有源层，具有至少两个固相和覆盖存储材料的绝热材料层，其具有小于第一和第二电极的热导率的导热性。

77. 发明申请

US20070108430A1 Thermally contained/insulated phase change memory device and method (combined) 有权
标题翻译：含热/绝缘相变存储器件和方法（组合）
公开(公告)号：US20070108430A1
公开(公告)日：2007-05-17
申请号：US11338284
申请日：2006-01-24
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.
摘要翻译：具有改善的传热特性的记忆装置。该装置首先包括介电材料层; 第一和第二电极，垂直分离并具有相互相对的接触表面。相变存储元件被封装在电介质材料层内，包括位于电极之间并与之电接触的相变层，其中相变层的横向范围小于电极的横向范围。隔离材料位于相变层和电介质层之间，其中隔离材料的热导率低于介电材料的热导率。

78. 发明申请

US20070045708A1 Stacked bit line dual word line nonvolatile memory 有权
标题翻译：堆叠位线双字线非易失性存储器
公开(公告)号：US20070045708A1
公开(公告)日：2007-03-01
申请号：US11217659
申请日：2005-08-31
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/76
CPC分类号： H01L27/11206 , H01L21/76895 , H01L23/50 , H01L23/5252 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
摘要翻译：一种非易失性存储器件的布置，其具有至少一个在半导体衬底上层次级别堆叠的存储器件级，每个存储器级包括基本上设置在半导体衬底之上的氧化物层，基本上设置在氧化物层上方的多条字线; 基本上设置在所述氧化物层上方的多个位线; 基本上与字线电接触的多个通孔插塞和基本上设置在位线旁边的侧壁上且与多个位线侧壁反熔丝电介质基本上接触的抗熔丝电介质材料。

79. 发明授权

US07053406B1 One-time programmable read only memory and manufacturing method thereof 有权
标题翻译：一次性可编程只读存储器及其制造方法
公开(公告)号：US07053406B1
公开(公告)日：2006-05-30
申请号：US10907442
申请日：2005-04-01
申请人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

80. 发明授权

US06830952B2 Spacer chalcogenide memory method and device 有权
标题翻译：间隔硫属化物记忆法和装置
公开(公告)号：US06830952B2
公开(公告)日：2004-12-14
申请号：US10654684
申请日：2003-09-04
申请人： Hsiang Lan Lung
发明人： Hsiang Lan Lung
IPC分类号： H01L2100
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/124 , H01L45/144 , H01L45/1691 , Y10S438/90
摘要： The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.
摘要翻译：本发明包括用于形成包括可编程电阻材料合金的间隔物的存储单元器件的器件和方法。在权利要求书，说明书和附图中描述了本发明的特定方面。

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