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71. 发明授权

US5444302A Semiconductor device including multi-layer conductive thin film of polycrystalline material 失效
标题翻译：半导体器件包括多层导电薄膜的多晶材料
公开(公告)号：US5444302A
公开(公告)日：1995-08-22
申请号：US168506
申请日：1993-12-22
申请人： Takashi Nakajima , Hideo Miura , Hiroyuki Ohta , Noriaki Okamoto
发明人： Takashi Nakajima , Hideo Miura , Hiroyuki Ohta , Noriaki Okamoto
IPC分类号： H01L21/02 , H01L23/532 , H01L29/49 , H01L23/48 , H01L29/46
CPC分类号： H01L21/28097 , H01L21/28035 , H01L21/28518 , H01L21/28525 , H01L21/32053 , H01L21/76838 , H01L21/76877 , H01L21/823437 , H01L23/485 , H01L23/53257 , H01L23/53271 , H01L28/40 , H01L29/4925 , H01L29/4975 , H01L2924/0002 , Y10T117/10 , Y10T117/1004
摘要： In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
摘要翻译：例如，通过氧化硅膜5在半导体衬底4上的硅6氧化膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成栅电极2。在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的获得膜厚度。利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

72. 发明授权

US5229643A Semiconductor apparatus and semiconductor package 失效
标题翻译：半导体装置和半导体封装
公开(公告)号：US5229643A
公开(公告)日：1993-07-20
申请号：US735353
申请日：1991-07-24
申请人： Hiroyuki Ohta , Norio Ishitsuka , Akihiro Yaguchi , Sueo Kawai , Nobuo Owada , Shigeki Hirasawa
发明人： Hiroyuki Ohta , Norio Ishitsuka , Akihiro Yaguchi , Sueo Kawai , Nobuo Owada , Shigeki Hirasawa
IPC分类号： H01L23/34 , H01L23/367 , H01L23/433 , H01L23/495 , H01L27/00
CPC分类号： H01L23/49568 , H01L23/3677 , H01L23/433 , H01L23/4334 , H01L2224/16145 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10158 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2924/18161
摘要： The heat transfer path (the heat radiating portion) from a position very near the semiconductor device as the heat source to the surface of the semiconductor apparatus is made of a material having a large heat conductivity thereby to more rapidly transfer the heat generated in the p-n junction to the surface of the semiconductor apparatus or the outside. This arrangement can cope with that the calorific power is increased as the integration is increased. The formation of the good heat conductive material from the surface of the apparatus to the heat source through the multilayer structure film can be attained by means of the CVD technique.
摘要翻译：从作为热源的半导体装置非常接近的位置到半导体装置的表面的热传递路径（散热部）由具有大的导热性的材料制成，从而更快速地传递在pn中产生的热量结到半导体器件的表面或外部。这种布置可以应付随着集成度增加而增加热量。通过CVD技术可以获得从装置的表面到热源通过多层结构膜形成良好的导热材料。

73. 外观设计

USD685908S1 Endoscope 有权
公开(公告)号：USD685908S1
公开(公告)日：2013-07-09
申请号：US29399583
申请日：2011-08-16
申请人： Yasuo Funakoshi , Hiroyuki Ohta , Kiwamu Fujitani , To Chin , Ai Yonekura
设计人： Yasuo Funakoshi , Hiroyuki Ohta , Kiwamu Fujitani , To Chin , Ai Yonekura

74. 发明授权

US08186228B2 Strain measuring device 有权
标题翻译：应变测量装置
公开(公告)号：US08186228B2
公开(公告)日：2012-05-29
申请号：US13024368
申请日：2011-02-10
申请人： Hiroyuki Ohta , Hiromi Shimazu , Yohei Tanno
发明人： Hiroyuki Ohta , Hiromi Shimazu , Yohei Tanno
IPC分类号： G01L1/00
CPC分类号： G01L1/2293
摘要： A strain measuring device includes a bridge circuit comprising a p-type impurity diffused resistor as a strain detecting portion and a bridge circuit comprising an n-type impurity diffused resistor as a strain detecting portion in a semiconductor single crystalline substrate, Sheet resistance of the p-type impurity diffused resistor is 1.67 to 5 times higher than that of the n-type impurity diffused resistor. Furthermore, the impurity diffused resistor is configured to be a meander shape including strip lines and connecting portions.
摘要翻译：应变测量装置包括桥式电路，其包括作为应变检测部分的p型杂质扩散电阻器和包括在半导体单晶衬底中的作为应变检测部分的n型杂质扩散电阻器的桥式电路，p电阻值型杂质扩散电阻器比n型杂质扩散电阻器高1.67〜5倍。此外，杂质扩散电阻器被构造为包括带状线和连接部分的曲折形状。

75. 发明申请

US20120009750A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120009750A1
公开(公告)日：2012-01-12
申请号：US13240303
申请日：2011-09-22
申请人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
发明人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
摘要翻译：在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。在第二SiGe混晶层上形成第三p型SiGe混晶层。从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

76. 发明授权

US08056421B2 Apparatus for measuring a mechanical quantity 有权
标题翻译：用于测量机械量的装置
公开(公告)号：US08056421B2
公开(公告)日：2011-11-15
申请号：US12719977
申请日：2010-03-09
申请人： Takashi Sumigawa , Hiroyuki Ohta
发明人： Takashi Sumigawa , Hiroyuki Ohta
IPC分类号： G01B7/16
CPC分类号： G01B7/18 , G01B7/16 , G01B7/20 , G01L1/2206 , G01L1/2262 , G01L5/0047
摘要： An apparatus structure and measurement method are provided to retain high precision and high reliability of a semiconductor mechanical quantity measuring apparatus which senses a mechanical quantity and transmits measured information wirelessly. As to a silicon substrate of the semiconductor mechanical quantity measuring apparatus, for example, a ratio of a substrate thickness to a substrate length along a measurement direction is set small, and a ratio of a substrate thickness to a substrate length along a direction perpendicular to the measurement direction is set small. The apparatus upper surface is covered with a protective member. It is possible to measure a strain along a particular direction and realize mechanical quantity measurement with less error and high precision. An impact resistance and environment resistance of the apparatus itself can be improved.
摘要翻译：提供了一种装置结构和测量方法，以保持半导体机械量测量装置的高精度和高可靠性，该装置检测机械量并无线传送测量信息。对于半导体机械量测量装置的硅衬底，例如，沿着测量方向将衬底厚度与衬底长度的比率设置得较小，并且沿着垂直于半导体机械量测量装置的方向的衬底厚度与衬底长度的比率测量方向设定得很小。设备上表面被保护构件覆盖。可以测量特定方向的应变，实现误差小，精度更高的机械量测量。可以提高装置本身的耐冲击性和耐环境性。

77. 发明授权

US07968414B2 Semiconductor device and production method thereof 有权
公开(公告)号：US07968414B2
公开(公告)日：2011-06-28
申请号：US12698303
申请日：2010-02-02
申请人： Hiroyuki Ohta , Takashi Sakuma , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Hiroyuki Ohta , Takashi Sakuma , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

78. 发明申请

US20110136307A1 SEMICONDUCTOR DEVICE HAVING BUFFER LAYER BETWEEN SIDEWALL INSULATING FILM AND SEMICONDUCTOR SUBSTRATE 有权
标题翻译：具有平板绝缘膜和半导体基板之间的缓冲层的半导体器件
公开(公告)号：US20110136307A1
公开(公告)日：2011-06-09
申请号：US13024988
申请日：2011-02-10
申请人： Hiroyuki OHTA , Katsuaki OOKOSHI
发明人： Hiroyuki OHTA , Katsuaki OOKOSHI
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1083 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.
摘要翻译：半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间。栅电极具有第一侧壁绝缘膜。另一个栅电极具有第二侧壁绝缘膜。第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

79. 发明申请

US20110121315A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110121315A1
公开(公告)日：2011-05-26
申请号：US12893664
申请日：2010-09-29
申请人： Hiroyuki Ohta , Yosuke Shimamune
发明人： Hiroyuki Ohta , Yosuke Shimamune
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/28097 , H01L21/823814 , H01L29/165 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.
摘要翻译：在pMOS区域和nMOS区域中形成沿着侧壁的凹部。在凹部中形成厚度比凹部深度厚的SiC层。覆盖SiC层的一部分的侧壁形成在pMOS区域中的栅电极的两侧。通过选择性去除pMOS区域中的SiC层形成凹陷。在栅极绝缘膜侧的凹部的侧面倾斜，使得侧面的上部区域在低于硅基板的表面的区域中在横向方向上越接近栅极绝缘膜。在pMOS区域的凹部中形成SiGe层。

80. 发明授权

US07893810B2 Strain measuring device 有权
标题翻译：应变测量装置
公开(公告)号：US07893810B2
公开(公告)日：2011-02-22
申请号：US11844374
申请日：2007-08-24
申请人： Hiroyuki Ohta , Hiromi Shimazu , Yohei Tanno
发明人： Hiroyuki Ohta , Hiromi Shimazu , Yohei Tanno
IPC分类号： G01L1/22
CPC分类号： G01L1/2293
摘要： A strain measuring device according to the present invention includes a bridged circuit comprising a p-type impurity diffused resistor as a strain detective portion and a bridged circuit comprising an n-type impurity diffused resistor as a strain detective portion in a semiconductor single crystalline substrate, and sheet resistance of the p-type impurity diffused resistor is 1.67 to 5 times higher than that of the n-type impurity diffused resistor. Furthermore, it is preferable that the impurity diffused resistor be configured to be a meander shape comprising strip lines and connecting portions. Moreover, it is preferable that the number of strip lines in the p-type impurity diffused resistor be smaller than that in the n-type impurity diffused resistor.
摘要翻译：根据本发明的应变测量装置包括：桥接电路，包括作为应变检测部分的p型杂质扩散电阻器和包括作为半导体单晶衬底中的应变检测部分的n型杂质扩散电阻器的桥接电路， p型杂质扩散电阻器的薄层电阻比n型杂质扩散电阻器的薄层电阻高1.67〜5倍。此外，优选地，杂质扩散电阻器被构造为包括带状线和连接部分的曲折形状。此外，优选的是，p型杂质扩散电阻器中的带状线的数量小于n型杂质扩散电阻器中的带状线数。

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