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71. 发明授权

US09059887B2 Receiving device and receiving method for determining doppler frequency from pilot signals using OFDM 有权
标题翻译：使用OFDM从导频信号确定多普勒频率的接收装置和接收方法
公开(公告)号：US09059887B2
公开(公告)日：2015-06-16
申请号：US13870572
申请日：2013-04-25
申请人： FUJITSU LIMITED , FUJITSU SEMICONDUCTOR LIMITED
发明人： Masataka Umeda , Naoto Adachi
IPC分类号： H04L27/06 , H04L27/26
CPC分类号： H04L27/265 , H04L5/0048 , H04L25/0222 , H04L27/2657 , H04L27/2675 , H04L27/2695
摘要： A receiving device for receiving OFDM signals in which arrangement of pilot signals changes with symbol time, includes: an inverse Fourier transform unit configured to calculate an impulse response by performing an inverse Fourier transform on pilot signals included in a received signal; a first Doppler frequency estimation unit configured to estimate a first Doppler frequency from a phase rotation amount at peak positions between impulse responses of pilot signals of different subcarriers of the impulse responses; a second Doppler frequency estimation unit configured to estimate a second Doppler frequency from a phase rotation amount between impulse responses of pilot signals of the same subcarrier of the impulse responses; and a Doppler frequency selection unit configured to select one of the first and the second Doppler frequency estimated by the first and the second Doppler frequency estimation unit so as to reduce influence of a multipath.
摘要翻译：一种接收装置，用于接收导频信号的配置以符号时间改变的OFDM信号，包括：傅里叶逆变换单元，被配置为通过对包括在接收信号中的导频信号执行傅里叶逆变换来计算脉冲响应; 第一多普勒频率估计单元，被配置为从脉冲响应的不同子载波的导频信号的脉冲响应之间的峰值位置处的相位旋转量估计第一多普勒频率; 第二多普勒频率估计单元，被配置为从脉冲响应的相同子载波的导频信号的脉冲响应之间的相位旋转量估计第二多普勒频率; 以及多普勒频率选择单元，被配置为选择由第一和第二多普勒频率估计单元估计的第一和第二多普勒频率中的一个，以减少多径的影响。

72. 发明授权

US09059033B2 Semiconductor device with pads of enhanced moisture blocking ability 有权
标题翻译：具有提高防潮能力的垫片的半导体器件
公开(公告)号：US09059033B2
公开(公告)日：2015-06-16
申请号：US14532311
申请日：2014-11-04
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kaoru Saigoh , Kouichi Nagai
IPC分类号： H01L23/52 , H01L27/115 , H01L23/00
CPC分类号： H01L27/11507 , H01L23/3157 , H01L23/522 , H01L23/564 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/11509 , H01L28/55 , H01L28/65 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05018 , H01L2224/05027 , H01L2224/05082 , H01L2224/05083 , H01L2224/05093 , H01L2224/05096 , H01L2224/05124 , H01L2224/05164 , H01L2224/05166 , H01L2224/05554 , H01L2224/05556 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05624 , H01L2224/05664 , H01L2224/05666 , H01L2224/1134 , H01L2224/1146 , H01L2224/13007 , H01L2224/13014 , H01L2224/13021 , H01L2224/13023 , H01L2224/13144 , H01L2224/45124 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48724 , H01L2224/48764 , H01L2224/48766 , H01L2224/49171 , H01L2224/49173 , H01L2924/00014 , H01L2924/0002 , H01L2924/01007 , H01L2924/01013 , H01L2924/01022 , H01L2924/05042 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2924/01029 , H01L2924/01046 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
摘要翻译：提供了一种具有改善的防潮能力的垫的半导体器件。半导体器件具有：包括形成在半导体衬底上的多个半导体元件的电路部分; 覆盖电路部分的绝缘体层叠，包括具有开口的最上层的钝化膜; 在绝缘子层压中形成的铁电电容器; 在绝缘体层叠形成并连接到半导体元件和铁电电容器的布线结构; 连接到布线结构的焊盘电极，形成在绝缘体的层叠中并暴露在钝化膜的开口中; 包括Pd膜的导电焊盘保护膜，通过钝化膜的开口覆盖每个焊盘电极，并在钝化膜上延伸; 以及通过导电焊盘保护膜连接到焊盘电极的螺柱凸块或接合线。

73. 发明授权

US09054732B2 SAR analog-to-digital conversion method and SAR analog-to-digital conversion circuit 有权
标题翻译： SAR模数转换方法和SAR模数转换电路
公开(公告)号：US09054732B2
公开(公告)日：2015-06-09
申请号：US14249973
申请日：2014-04-10
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Tomoya Kakamu
IPC分类号： H03M1/38 , H03M1/12 , H03M1/46 , H03M1/44
CPC分类号： H03M1/38 , H03M1/129 , H03M1/162 , H03M1/206 , H03M1/44 , H03M1/468
摘要： An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at ¼ or ¾ of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.
摘要翻译： SAR模数转换电路包括：第一和第二CDAC; 分别比较第一和第二CDAC的输出，第一和第三CDAC的输出电平与参考电平的第一至第三比较器; 算术运算电路; SAR控制电路，其中所述SAR控制电路：在每个步骤中确定在四个范围中的哪一个范围中包括所述第一和第二CDAC的采样和保持的信号的输出电平，与所述转换范围相对应的四个范围被分配，确定数字数据的两位，并调整第一和第二CDAC的输出电平，使得电压范围的1/4或¾的电平与中间电平一致，并且控制第一和第二开关，使得电压范围被设置为作为下一步的转换范围。

74. 发明申请

US20150155872A1 SEMICONDUCTOR DEVICE AND COMMUNICATION INTERFACE CIRCUIT 有权
标题翻译：半导体器件和通信接口电路
公开(公告)号：US20150155872A1
公开(公告)日：2015-06-04
申请号：US14550725
申请日：2014-11-21
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Daisuke SUZUKI , Masayuki YAMAGUCHI
IPC分类号： H03K19/0175 , H03K19/173
CPC分类号： H03K19/017581 , H03K19/017509 , H03K19/1736
摘要： A communication interface circuit includes a register and a register setting circuit. The register holds a data value for controlling characteristics of an electronic circuit element included in the communication interface circuit. The register setting circuit changes a wire connection state on the basis of a control signal. The register setting circuit inputs a variable data value to the register to detect the data value corresponding to the characteristics of the electronic circuit element in a first wire connection state, and sets the data value detected in the first wire connection state in the register on the basis of a fixed value in a second wire connection state. A control circuit outputs the above control signal.
摘要翻译：通信接口电路包括寄存器和寄存器设置电路。寄存器保持用于控制通信接口电路中包括的电子电路元件的特性的数据值。寄存器设定电路根据控制信号改变接线状态。寄存器设定电路向寄存器输入可变数据值，以检测与第一有线连接状态下的电子电路元件的特性对应的数据值，并将在第一线连接状态中检测到的数据值设置在寄存器中在第二线连接状态下的固定值的基础。控制电路输出上述控制信号。

75. 发明授权

US09036724B2 Data signal correction circuit, receiver, and data signal correction method 有权
标题翻译：数据信号校正电路，接收器和数据信号校正方法
公开(公告)号：US09036724B2
公开(公告)日：2015-05-19
申请号：US14179285
申请日：2014-02-12
申请人： FUJITSU SEMICONDUCTOR LIMITED , FUJITSU LIMITED
发明人： Hiroaki Takagi , Masataka Umeda , Naoto Adachi
IPC分类号： H04K1/10 , H04L25/02 , H04L25/03
CPC分类号： H04L25/0212 , H04L25/0204 , H04L25/022 , H04L25/0232 , H04L25/0236 , H04L25/03019 , H04L2025/03636
摘要： A data signal correction circuit includes a channel characteristic calculator unit configured to calculate a channel characteristic estimate value of a received data signal on the basis of a pilot signal, a path detector unit configured to determine a delay quantity of multipath propagation of the received data signal on the basis of the calculated channel characteristic estimate value, and an adaptive filter configured to receive the delay quantity and the channel characteristic estimate value as input items, adjust an input interval of the channel characteristic estimate value along a carrier frequency axis in accordance with the delay quantity, and perform adaptive equalization on the channel characteristic estimate value inputted to the adaptive filter at the adjusted input interval.
摘要翻译：数据信号校正电路包括：信道特性计算单元，被配置为基于导频信号计算接收数据信号的信道特性估计值;路径检测器单元，被配置为确定接收数据信号的多径传播的延迟量以及被配置为接收所述延迟量和所述信道特性估计值作为输入项的自适应滤波器，根据所述信道特性估计值沿着载波频率轴调整所述信道特性估计值的输入间隔，对调整后的输入间隔输入到自适应滤波器的信道特性估计值进行自适应均衡。

76. 发明申请

US20150130540A1 AMPLIFIER 有权
标题翻译：放大器
公开(公告)号：US20150130540A1
公开(公告)日：2015-05-14
申请号：US14530028
申请日：2014-10-31
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Nobumasa HASEGAWA
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F1/0266 , H03F1/3211 , H03F3/245 , H03F3/45475 , H03F2200/411 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/555 , H03F2203/45051 , H03F2203/45112 , H03F2203/45228 , H03F2203/45244
摘要： An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.
摘要翻译：放大器包括被配置为输出第一差分信号的第一变压器，耦合到第一变压器的第一差分放大器，耦合到第一差分放大器的第二变压器，耦合到第二变压器的第二差分放大器，被配置为转换第二变换器差分信号从第二差分放大器输出到单端输出信号，以及第一偏置电路，其被配置为向第一变压器的第一次级线圈提供第一偏置电压，其中第一偏置电路将第一偏置电压设置为基于在输出信号的功率大于或等于第一功率的第一操作区域中的输入信号的电压大于或等于第一电压，使得输出信号的功率增益特性变得更接近于其中增益的输出信号变为恒定。

77. 发明授权

US09012285B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09012285B2
公开(公告)日：2015-04-21
申请号：US13765266
申请日：2013-02-12
申请人： Fujitsu Semiconductor Limited
发明人： Akihiro Usujima , Shigeo Satoh
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
摘要翻译：半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁隔离物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

78. 发明申请

US20150098263A1 FERROELECTRIC MEMORY DEVICE 有权
标题翻译：电磁存储器件
公开(公告)号：US20150098263A1
公开(公告)日：2015-04-09
申请号：US14485494
申请日：2014-09-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Tomohisa HIRAYAMA , Keizo Morita , Naoharu Shinozaki
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/5657 , H03M13/09 , H03M13/1148 , H03M13/118 , H03M13/19
摘要： A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.
摘要翻译：铁电存储器件包括存储器阵列，其包括多个铁电存储器单元，代码生成电路，被配置为乘数写入数据和奇偶校验生成器矩阵以产生校验位，由此产生具有信息位的汉明码和布置在其中的校验位，所述信息位是所述写入数据，以及驱动器电路，被配置为将所述汉明码写入所述存储器阵列，其中所述奇偶校验生成矩阵具有多个行，并且每行中的“1”的数量是偶数数。

79. 发明申请

US20150095871A1 CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：电路设计支持方法，计算机产品，电路设计支持设备和半导体集成电路
公开(公告)号：US20150095871A1
公开(公告)日：2015-04-02
申请号：US14497876
申请日：2014-09-26
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Tomoyasu Kitaura
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G06F17/5077 , G06F2217/62 , G06F2217/84 , H01L27/0207 , H01L2027/11877
摘要： A circuit design support method includes obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
摘要翻译：一种电路设计支持方法，包括获得布置数据，该布局数据指示布置在电路中的多个时钟接收器的位置和设置在电路中的第一时钟线的位置; 并且通过计算机根据所获得的布局数据，计算对应于分别将时钟接收器连接到第二时钟线的线的长度的值，该值针对第二时钟的计数的多个组合中的每一个计算第二时钟线的导线和位置，第二时钟线布置在电路的布线层中并垂直于第一时钟线。

80. 发明申请

US20150084160A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150084160A1
公开(公告)日：2015-03-26
申请号：US14557836
申请日：2014-12-02
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Wensheng WANG
IPC分类号： H01L49/02
CPC分类号： H01L28/56 , H01L27/11507
摘要： A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.
摘要翻译：形成在半导体衬底上的铁电电容器包括下电极，具有铁电特性的电介质膜（铁电体膜）和上电极。上电极包括由铁电材料制成的导电氧化膜，通过添加诸如Ir的导电材料提供导电性，并且导电氧化物膜与电介质膜接触。

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