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71. 发明申请

US20190052261A1 Adaptive Body Biasing In CMOS Circuits To Extend The Input Common Mode Operating Range 审中-公开
公开(公告)号：US20190052261A1
公开(公告)日：2019-02-14
申请号：US16160552
申请日：2018-10-15
申请人： Exar Corporation
发明人： Vinit JAYARAJ , Pekka OJALA , John TABLER
IPC分类号： H03K17/30 , H03K17/06
CPC分类号： H03K17/302 , H03K17/063 , H03K2217/0018
摘要： In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

72. 发明申请

US20180287604A1 ADAPTIVE BODY BIASING IN CMOS CIRCUITS TO EXTEND THE INPUT COMMON MODE OPERATING RANGE 审中-公开
公开(公告)号：US20180287604A1
公开(公告)日：2018-10-04
申请号：US15474791
申请日：2017-03-30
申请人： Exar Corporation
发明人： Vinit JAYARAJ , Pekka OJALA , John TABLER
IPC分类号： H03K17/30
摘要： In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

73. 发明授权

US10056890B2 Digital controlled oscillator based clock generator for multi-channel design 有权
公开(公告)号：US10056890B2
公开(公告)日：2018-08-21
申请号：US15192970
申请日：2016-06-24
申请人： Exar Corporation
发明人： Omeshwar Lawange
IPC分类号： H03K21/00 , H03K5/14 , H03K21/10 , H03K3/037 , H03K23/66 , H03K23/68 , H03K5/00
CPC分类号： H03K5/14 , H03K3/037 , H03K21/10 , H03K23/66 , H03K23/68 , H03K2005/00058
摘要： A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

74. 发明申请

US20170373674A1 DIGITAL CONTROLLED OSCILLATOR BASED CLOCK GENERATOR FOR MULTI-CHANNEL DESIGN 审中-公开
公开(公告)号：US20170373674A1
公开(公告)日：2017-12-28
申请号：US15192970
申请日：2016-06-24
申请人： Exar Corporation
发明人： OMESHWAR LAWANGE
IPC分类号： H03K5/14 , H03K3/037 , H03K21/10 , H03K5/00
CPC分类号： H03K5/14 , H03K3/037 , H03K21/10 , H03K23/66 , H03K23/68 , H03K2005/00058
摘要： A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

75. 发明申请

US20170363450A1 METHOD AND APPARATUS FOR MULTI-CHANNEL SENSOR INTERFACE WITH PROGRAMMABLE GAIN, OFFSET AND BIAS 有权
公开(公告)号：US20170363450A1
公开(公告)日：2017-12-21
申请号：US15187730
申请日：2016-06-20
申请人： Exar Corporation
发明人： Steven Smith , Dale Wedel
IPC分类号： G01D18/00 , G01D5/16
CPC分类号： G01D18/008 , G01D5/16 , G05B19/0423
摘要： A highly integrated programmable sensor interface with improved sensor signal calibration and conditioning functions is described. The programmable sensor interface according to the present invention sensor interface provides programmable gain, digital offset correction and bias for one or more signal channels on one chip on a per channel basis. According to another aspect of the invention, the sensor interface provides reference voltage and sensor biasing by using an on-chip precision voltage regulator. According to one aspect of the invention, multiple inputs are multiplexed and each is applied to a variable gain instrumentation amplifier, which connects to the output. The offset of a given channel is controlled by an on-chip DAC which has multiple digital storage registers, allowing each channel to have a unique, stored offset. Offsets and gains are programmed externally.

76. 发明申请

US20040155700A1 CMOS bandgap reference with low voltage operation 失效
标题翻译： CMOS带隙参考低电压工作
公开(公告)号：US20040155700A1
公开(公告)日：2004-08-12
申请号：US10364278
申请日：2003-02-10
申请人： Exar Corporation
发明人： Richard Leigh Gower , Bhupendra Kumar Ahuja
IPC分类号： G05F001/10 , G05F003/02
CPC分类号： G05F3/30
摘要： A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to include a multitude of output stages. Each output stage may be independently scaled to sum any selected multiple of the first current to any selected multiple of the second current to generate an output voltage having either a nearly zero, a positive or a negative temperature coefficient. For example, the first output stage may be scaled to generate a reference output voltage with a nearly zero temperature coefficient. Similarly, the second output stage may be scaled to generate a reference output voltage with a negative temperature coefficient.
摘要翻译：带隙参考电压发生器部分地包括具有第一运算放大器并适于产生具有正温度系数的第一电流的第一闭环电路和具有第二运算放大器的第二闭环电路，并且适于产生具有负温度系数的第二电流。带隙参考电压发生器还适于包括多个输出级。每个输出级可以被独立地缩放以将第一电流的任何选定倍数与第二电流的任何选定倍数相加以产生具有接近零，正或负温度系数的输出电压。例如，可以缩放第一输出级以产生具有接近零温度系数的参考输出电压。类似地，第二输出级可以被缩放以产生具有负温度系数的参考输出电压。

77. 发明申请

US20040080359A1 LOOP FILTER CAPACITOR MULTIPLICATION IN A CHARGE PUMP CIRCUIT 有权
标题翻译：充电泵电路中的环路滤波电容器多路复用
公开(公告)号：US20040080359A1
公开(公告)日：2004-04-29
申请号：US10280314
申请日：2002-10-25
申请人： Exar Corporation
发明人： Shin Chung Chen , Vincent Wing Sing Tso
IPC分类号： G05F001/10
CPC分类号： H03L7/0896 , H03H11/483 , H03L7/0893
摘要： A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.
摘要翻译：本发明公开了一种具有小环路滤波电容器的电荷泵电路。这通过提供多个电流来实现，该电流增加了所需的电流I.开关电路通过电容器切换电流中的一个，同时引导多个电流的组合通过电阻器。以这种方式，通过电容器提供较小的电流，允许电容器的尺寸要小得多。

78. 发明申请

US20030197996A1 BOUNCE TOLERANT FUSE TRIMMING CIRCUIT WITH CONTROLLED TIMING 失效
标题翻译：具有受控时序的耐压保险丝修复电路
公开(公告)号：US20030197996A1
公开(公告)日：2003-10-23
申请号：US10118687
申请日：2002-04-08
申请人： Exar Corporation
发明人： Andras Szabo , Pekka Ojala
IPC分类号： H02H005/04
CPC分类号： G11C17/18
摘要： A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The delay structure also provides a pass filter to filter power and voltage spikes in the select signal.
摘要翻译：一种实现微调电路的方法和装置。更具体地说，本发明的实施例提供了一种晶体管，当晶体管通电时，以及在其栅极接收到选择信号之后，提供足够的电流来修整微调熔丝。当修整保险丝被修整时，它会将电路中的不需要的电气连接断开。还提供了将RC延迟添加到选择信号的延迟结构。 RC延迟具有足够长的持续时间，从而降低晶体管的开关速度。延迟结构还提供了一个通过滤波器来滤除选择信号中的功率和电压尖峰。

79. 发明申请

US20030071660A1 POWER DOWN CIRCUIT FOR HIGH OUTPUT IMPEDENCE STATE OF I/O DRIVER 有权
标题翻译：用于I / O驱动器的高输出阻抗状态的掉电电路
公开(公告)号：US20030071660A1
公开(公告)日：2003-04-17
申请号：US09978255
申请日：2001-10-15
申请人： Exar Corporation
发明人： Loi Thanh Le , Pekka Ojala , Bahram Fotouhi
IPC分类号： H03B001/00
CPC分类号： H03K19/00315
摘要： A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the Pnull/n-well diode.
摘要翻译：一种用于在电源故障时将输出驱动器置于高阻态的电路。这是通过提供连接在电源和n阱之间以对PMOS驱动晶体管的n阱节点充电的第一晶体管来实现的。当电源电压失效时，连接多个晶体管以将n阱和PMOS驱动晶体管的栅极耦合到输出线，使得它们跟踪输出的电压电平，从而防止P + / n阱二极管。

80. 发明申请

US20020109533A1 AUTOMATIC FREQUENCY RATE SWITCH 有权
标题翻译：自动频率开关
公开(公告)号：US20020109533A1
公开(公告)日：2002-08-15
申请号：US09782789
申请日：2001-02-13
申请人： Exar Corporation
发明人： Roubik Gregorian , Manop Thamsirianunt
IPC分类号： H03K003/00
CPC分类号： H03K5/08 , H03K5/13 , H03K5/135 , H03K2005/00156 , H03K2005/00202 , H04L25/0262 , H04L29/06 , H04L69/18 , H04L69/323
摘要： A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated. This may be simply the appropriate frequency, but, depending upon the chip, may include pulse shaping, framing and other configuration selections.
摘要翻译：一种用于根据所施加时钟的频率自动确定正在使用的协议的方法和装置，而不需要单独的引脚或开关或第二外部时钟。当其频率落入设备所针对的设定范围内时，识别时钟的频率。基于检测到的设定范围内的频率，生成模式选择信号。模式选择信号使芯片配置为该模式的适当频率，以及任何其他唯一的配置参数。在一个实施例中，本发明产生由外部时钟（其是期望协议的时钟频率）触发的斜坡信号。时钟同时应用于计数器。当斜坡信号达到参考电压时，将计数器的计数与至少一个阈值进行比较，以确定其对应的频率。响应于该确定，芯片根据指示的通信模式或协议进行配置。这可能只是适当的频率，但是，取决于芯片，可能包括脉冲整形，成帧和其他配置选择。

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