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71. 发明授权

US06750069B2 Minimally spaced MRAM structures 有权
标题翻译：最小间隔的MRAM结构
公开(公告)号：US06750069B2
公开(公告)日：2004-06-15
申请号：US10454479
申请日：2003-06-05
申请人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
发明人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
IPC分类号： H01L21336
CPC分类号： H01L27/222 , B82Y10/00
摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
摘要翻译：公开了形成最小间隔的MRAM结构的方法。使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

72. 发明授权

US06620680B2 Method of forming a contact structure and a container capacitor structure 有权
公开(公告)号：US06620680B2
公开(公告)日：2003-09-16
申请号：US10080465
申请日：2002-02-22
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10852 , H01L28/91
摘要： Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

73. 发明授权

US06423621B1 Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same 有权
公开(公告)号：US06423621B1
公开(公告)日：2002-07-23
申请号：US09964145
申请日：2001-09-25
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L2144
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

74. 发明授权

US06391735B1 Container capacitor structure 失效
标题翻译：集装箱电容器结构
公开(公告)号：US06391735B1
公开(公告)日：2002-05-21
申请号：US09653226
申请日：2000-08-31
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹部，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质的部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

75. 发明授权

US06312988B1 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 失效
标题翻译：形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06312988B1
公开(公告)日：2001-11-06
申请号：US09389532
申请日：1999-09-02
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
IPC分类号： H01L218242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node. In yet another embodiment, a plurality of capacitor storage nodes are formed arranged in columns. A common cell electrode layer is formed over the plurality of capacitor storage nodes. Cell electrode layer material is removed from between the columns and isolates individual cell electrodes over individual respective capacitor storage nodes. After the removing of the cell electrode layer material, conductive material is formed over portions of remaining cell electrode material thereby placing some of the individual cell electrodes into electrical communication with one another.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。在另一个实施例中，电容器存储节点形成为具有与其接合的最上表面和侧表面。在最大表面上形成保护帽，并且在侧表面和保护盖上形成电容器电介质层。在电容器存储节点的侧表面上形成电池电极层。在另一个实施例中，形成多列电容器存储节点。在多个电容器存储节点上形成公共电极电极层。从柱之间移除电极电极层材料，并在各个电容器存储节点上隔离各个电池电极。在除去电池电极层材料之后，在剩余的电池电极材料的部分上形成导电材料，从而使一些单个电池电极彼此电连通。

76. 发明授权

US5376817A Structure for a semiconductor device comprising conductive trench sidewalls 失效
标题翻译：包括导电沟槽侧壁的半导体器件的结构
公开(公告)号：US5376817A
公开(公告)日：1994-12-27
申请号：US194772
申请日：1994-02-09
申请人： Mirmajid Seyyedy , D. Mark Durcan
发明人： Mirmajid Seyyedy , D. Mark Durcan
IPC分类号： H01L27/02 , H01L23/40 , H01L23/48
CPC分类号： H01L27/0218
摘要： A structure for a semiconductor integrated circuit device comprises a p-type transistor and an n-type transistor, with each transistor having two diffusion regions. A trench interposed between the two transistors comprises a pair of conductively doped sidewalls. One sidewall is electrically coupled with power, and the other is electrically coupled with ground. A diffusion region from each transistor is electrically coupled with one of the sidewalls, with one transistor receiving power and the other receiving ground from the conductive sidewalls. The two transistor diffusion regions not electrically coupled with one of the sidewalls are electrically interconnected.
摘要翻译：半导体集成电路器件的结构包括p型晶体管和n型晶体管，每个晶体管具有两个扩散区域。夹在两个晶体管之间的沟槽包括一对导电掺杂的侧壁。一个侧壁与电力电耦合，另一个与地电耦合。来自每个晶体管的扩散区域与一个侧壁电耦合，一个晶体管接收功率，另一个晶体管从导电侧壁接收接地。不与一个侧壁电耦合的两个晶体管扩散区域电互连。

77. 发明授权

US5177027A Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path 失效
标题翻译：在硅台面的边缘上制造具有间隔物形栅极和直角沟道路径的MOSFET的工艺
公开(公告)号：US5177027A
公开(公告)日：1993-01-05
申请号：US569353
申请日：1990-08-17
申请人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
发明人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/762 , H01L21/8242 , H01L29/423
CPC分类号： H01L29/66477 , H01L21/02238 , H01L21/02255 , H01L21/2815 , H01L21/31662 , H01L21/76237 , H01L27/10873 , H01L29/66666 , H01L29/4236
摘要： A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gate oxide layer on the substrate and vertical sidewalls of the mesa; blanket deposition of a gate layer (typically polysilicon); anisotropically etching the gate layer to expose the upper surface of the mesa and leave a stringer gate around the circumference thereof; and doping the upper surface of the mesa and regions of the substrate peripheral to the circumferential polysilicon stringer to create source and drain regions. The standard process provides device density approximately double that of standard FET fabrication processes. Density can be increased even further by increasing the number of silicon mesas with a minimum pitch distance. This may be accomplished by employing the reduced-pitch masking technique disclosed in a copending U.S. patent application. Multiple transistors may be created on a single mesa by creating isolation regions within the mesa. The circumferential gate may be severed so as to provide a pair of gate inputs for transistors created on a single mesa. Enhancements common to conventional MOSFETS, such as lightly-doped source and drains, halos, etc., may be utilized for the new MOSFET process.
摘要翻译：在硅台面的或多或少垂直边缘上制造具有间隔物形栅极和直角沟道路径的MOS场效应晶体管的工艺。该方法包括以下步骤：在平面硅衬底上产生凸起区域（台面）; 在基板上形成栅极氧化物层和台面的垂直侧壁; 栅极层（通常为多晶硅）的覆盖沉积; 各向异性地蚀刻栅极层以暴露台面的上表面并且围绕其周边留下纵梁; 并且将周向多晶硅桁条外围的台面的上表面和基板的区域掺杂以产生源区和漏区。标准工艺提供的器件密度约为标准FET制造工艺的两倍。通过增加具有最小间距距离的硅台面的数量，可进一步增加密度。这可以通过采用共同未决的美国专利申请中公开的减少节距掩蔽技术来实现。可以通过在台面内创建隔离区域，在单个台面上创建多个晶体管。可以切断周向栅极，以便为在单个台面上产生的晶体管提供一对栅极输入。对于新的MOSFET工艺，可以使用传统MOSFETs通用的增强功能，例如轻掺杂源极和漏极，卤素等。

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