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71. 发明授权

US07593271B2 Memory device including multiplexed inputs 失效
标题翻译：存储器件包括复用输入
公开(公告)号：US07593271B2
公开(公告)日：2009-09-22
申请号：US11744815
申请日：2007-05-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C7/10
CPC分类号： G11C5/066 , G11C8/06
摘要： Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.
摘要翻译：描述了用于减少半导体封装上的外部触点数量的系统和方法，而不减少集成电路内部对半导体封装使用的地址，数据和控制信号的数量。在一些实施例中，可以在共享导体处接收两个信号，所述共享导体可由半导体封装外部的器件访问，并且传送到集成电路上对半导体封装的外部不可访问的两个触点。在各种实施例中，使用减少数量的外部触点来传送支持JEDEC JESD79E标准或JEDEC JESD79-2C标准的全部特征所需的信号。

72. 发明授权

US07444575B2 Architecture and method for testing of an integrated circuit device 有权
标题翻译：集成电路设备测试的架构和方法
公开(公告)号：US07444575B2
公开(公告)日：2008-10-28
申请号：US11207518
申请日：2005-08-19
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31926 , G01R31/31723 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31917
摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
摘要翻译：在一个实施例中，本发明提供了一种硬件和/或软件平台，其能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。该平台可以包括测试部件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶片探针程序，负载板和外部测试设备的相关硬件以及软件和例程用于最终测试程序。

73. 发明授权

US07443188B2 Electronic device having an interface supported testing mode 有权
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：US07443188B2
公开(公告)日：2008-10-28
申请号：US11981854
申请日：2007-10-31
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a logic device and an integrated circuit disposed within a semiconductor device package. The logic device may be configured to operate in at least a normal mode and a test mode. A terminal external to the semiconductor device package may be electronically coupled to the logic device and the integrated circuit. The terminal may be configured to operate as a shared input for the logic device and the integrated circuit. A multiplexer circuit may be configured to convey a first signal from the terminal to the logic device in the test mode, to convey a second signal from the integrated circuit to the logic device in the normal mode, and to receive a third signal from the integrated circuit for causing a transition between the normal mode and the test mode.
摘要翻译：提供一种用于测试逻辑器件和设置在半导体器件封装内的集成电路的系统。逻辑器件可以被配置为至少在正常模式和测试模式下操作。半导体器件封装外部的端子可以电连接到逻辑器件和集成电路。终端可以被配置为作为用于逻辑设备和集成电路的共享输入。多路复用器电路可以被配置为在测试模式中将来自终端的第一信号传送到逻辑设备，以在正常模式下将第二信号从集成电路传送到逻辑器件，并且从集成导致正常模式和测试模式之间转换的电路。

74. 发明授权

US07313740B2 Internally generating patterns for testing in an integrated circuit device 有权
标题翻译：内部生成集成电路设备中的测试模式
公开(公告)号：US07313740B2
公开(公告)日：2007-12-25
申请号：US11083473
申请日：2005-03-18
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G01R31/31813 , G11C2029/3602 , H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49109 , H01L2224/49175 , H01L2924/01021 , H01L2924/01055 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
摘要翻译：在与第二集成电路芯片一起包含在单个封装中的第一集成电路芯片中，系统包括第一集成电路芯片上的电路，用于在正常操作期间从第二集成电路芯片接收地址信号。第一集成电路芯片上的电路产生用于在测试模式下测试第一集成芯片的地址信号。

75. 发明授权

US07310000B2 Integrated circuit testing module including command driver 有权
标题翻译：集成电路测试模块包括命令驱动程序
公开(公告)号：US07310000B2
公开(公告)日：2007-12-18
申请号：US11443872
申请日：2006-05-30
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/31922 , G11C29/1201 , G11C29/48 , G11C29/56 , G11C29/56004 , G11C29/56012 , G11C2029/5602 , G11C2029/5606 , G11C2207/104
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
摘要翻译：公开了测试集成电路的系统和方法。该系统包括被配置为在自动测试设备和要测试的集成电路之间操作的测试模块。测试接口被配置为以比自动化测试设备配置为运行的更高的时钟频率测试集成电路。为了这样做，测试接口包括被配置用于生成要提供给集成电路的地址和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。

76. 发明申请

US20070263458A1 Memory Device Including Multiplexed Inputs 失效
标题翻译：包含复用输入的存储器
公开(公告)号：US20070263458A1
公开(公告)日：2007-11-15
申请号：US11744815
申请日：2007-05-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C7/10
CPC分类号： G11C5/066 , G11C8/06
摘要： Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.
摘要翻译：描述了用于减少半导体封装上的外部触点数量的系统和方法，而不减少集成电路内部对半导体封装使用的地址，数据和控制信号的数量。在一些实施例中，可以在共享导体处接收两个信号，该共享导体可由半导体封装外部的器件访问，并且传送到集成电路上对半导体封装的外部不可访问的两个触点。在各种实施例中，使用减少数量的外部触点来传送支持JEDEC JESD79E标准或JEDEC JESD79-2C标准的全部特征所需的信号。

77. 发明授权

US07245141B2 Shared bond pad for testing a memory within a packaged semiconductor device 有权
标题翻译：用于测试封装的半导体器件内的存储器的共用焊盘
公开(公告)号：US07245141B2
公开(公告)日：2007-07-17
申请号：US11223286
申请日：2005-09-09
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G01R31/26
CPC分类号： G01R31/31723 , G01R31/31701 , G01R31/3172 , G01R31/318513 , G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/3602 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.
摘要翻译：提供了一种用于通过其共享的外部端子与封装的半导体器件内的器件通信的系统。作为一个示例，系统提供测试包内的存储器。除了设备和共享外部终端之外，系统还包括一个接收多个命令信号的命令寄存器，以及耦合在外部终端和命令寄存器之间的数字逻辑器件。每个数字逻辑器件接收不同的时钟信号，并将命令信号之一输出到命令寄存器。以与时钟信号协调的顺序将命令信号提供给外部终端，使得每个数字逻辑设备缓冲命令信号之一。

78. 发明授权

US07103815B2 Testing of integrated circuit devices 有权
标题翻译：集成电路器件测试
公开(公告)号：US07103815B2
公开(公告)日：2006-09-05
申请号：US10870365
申请日：2004-06-17
申请人： Adrian E. Ong , Fan Ho
发明人： Adrian E. Ong , Fan Ho
IPC分类号： G11C29/00 , G06F7/02 , H04L7/00
CPC分类号： G11C29/12015 , G01R31/31715 , G01R31/31727 , G01R31/3187 , G11C29/1201 , G11C29/48 , G11C29/56 , G11C29/56012
摘要： An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
摘要翻译：集成电路装置包括耦合到外部连接器的数据缓冲器，在外部连接器上提供数据信号。耦合到数据缓冲器的测试缓冲器接收数据信号并向延迟电路提供测试输出信号。延迟电路以集成电路器件内部的第一时钟速率接收测试输出信号，并将测试输出信号中的测试数据与预期测试信号值进行比较。延迟电路以比第一时钟速率慢的第二时钟速率向外部连接器提供结果。

79. 发明授权

US07006940B1 Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip 失效
标题翻译：设置第一个集成电路芯片，以允许对共同封装的第二集成电路芯片进行测试
公开(公告)号：US07006940B1
公开(公告)日：2006-02-28
申请号：US10679673
申请日：2003-10-03
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G06F19/00
CPC分类号： G01R31/31723 , G01R31/31707 , G01R31/318513 , G11C5/04 , G11C29/1201 , G11C29/46 , G11C29/48 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2924/00014
摘要： A method and system are provided for testing a first integrated circuit chip which is packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are shared by the first and second integrated circuit chips. The method and system include: powering down the second integrated circuit chip; tri-stating a plurality of input/output (I/O) drivers of the second integrated circuit chip so that the plurality of I/O drivers do not drive any signals onto any connections for the shared external terminals; and performing testing of the first integrated circuit chip according to one or more regular testing routines.
摘要翻译：提供了一种用于测试在半导体器件中与至少第二集成电路芯片一起封装的第一集成电路芯片的方法和系统，其中半导体器件的至少一些外部端子由第一和第二集成电路芯片共享。该方法和系统包括：断电第二集成电路芯片; 三态表示第二集成电路芯片的多个输入/输出（I / O）驱动器，使得多个I / O驱动器不将任何信号驱动到用于共享外部端子的任何连接上; 以及根据一个或多个常规测试程序对第一集成电路芯片进行测试。

80. 发明授权

US06732304B1 Chip testing within a multi-chip semiconductor package 有权
标题翻译：多芯片半导体封装内的芯片测试
公开(公告)号：US06732304B1
公开(公告)日：2004-05-04
申请号：US09666208
申请日：2000-09-21
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C2900
CPC分类号： G11C29/1201 , G11C29/48 , G11C2207/104
摘要： A system and method is provided for testing a secondary chip housed within a multi-chip packaged semiconductor device. The packaged semiconductor device includes a secondary chip and a primary chip, with the secondary chip communicating with the primary chip through signal drivers. The secondary chip also includes at least one test signal driver connected to the signal drivers and to certain external connectors that may be shared with the primary chip. The test signal drivers provide testing of the secondary chip using standard integrated circuit test equipment while the secondary chip is contained within the packaged semiconductor device.
摘要翻译：提供了一种用于测试容纳在多芯片封装半导体器件内的次级芯片的系统和方法。封装的半导体器件包括二次芯片和一次芯片，二次芯片通过信号驱动器与主芯片通信。次级芯片还包括连接到信号驱动器的至少一个测试信号驱动器以及可以与主芯片共享的某些外部连接器。测试信号驱动器使用标准集成电路测试设备提供对次级芯片的测试，而次级芯片包含在封装的半导体器件内。

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