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71. 发明专利

DE69822029D1 未知
公开(公告)号：DE69822029D1
公开(公告)日：2004-04-08
申请号：DE69822029
申请日：1998-04-01
申请人： ALLEGRO MICROSYSTEMS INC
发明人： MOODY KRISTANN L , VIG RAVI , SCHELLER P KARL , TOWNE JAY M , TU TERI L
IPC分类号： G01D3/02 , G01D5/244

72. 发明专利

DE19620548C2 未知
公开(公告)号：DE19620548C2
公开(公告)日：2001-10-18
申请号：DE19620548
申请日：1996-05-22
申请人： ALLEGRO MICROSYSTEMS INC
发明人： ENGEL RAYMOND W , VIG RAVI , GILBERT PETER J , TU TERI , CLAPP TERRY
IPC分类号： G01P3/488 , G01B7/00 , G01D5/14 , G01D5/245 , G01D11/24 , G01P3/487 , G01D5/20 , G01B7/30 , G01R33/07
摘要： This invention is a magnetic-field sensor assembly comprising a preformed housing shell having a first end which includes an opening, and a second end which includes a window and having a cylindrical shape with a flattened portion to produce a truncated circular cross-section, a sensor package including an integrated-circuit magnetic-field-sensor chip encapsulated in a protective body with first and second opposite and mutually parallel faces and a plurality of integral conductive leads, each lead having a proximal portion, a distal portion, and a central portion, the proximal portion of each of said plurality of leads extending from said body, the central portion of said plurality of leads extending away from the body and positioned substantially normal the faces of the body, said sensor-package body being positioned in said housing shell part way through said window with said one body face extending outwardly from said housing shell and with said lead distal portions extending from said housing shell through said opening, a magnet having a first end and a second end and positioned in said housing shell with said first end adjacent to said second sensor-package body face, and an endcap adapted to close said opening in said housing shell.

73. 发明专利

FR2744806B1 未知
公开(公告)号：FR2744806B1
公开(公告)日：2001-10-05
申请号：FR9701550
申请日：1997-02-11
申请人： ALLEGRO MICROSYSTEMS INC
发明人： VIG RAVI , TU TERI , LATHAM II PAUL W
IPC分类号： G01R33/07 , H03K3/0233

74. 发明专利

DE69425465T2 未知
公开(公告)号：DE69425465T2
公开(公告)日：2001-01-11
申请号：DE69425465
申请日：1994-05-18
申请人： ALLEGRO MICROSYSTEMS INC
发明人： VIG RAVI , YABUSAKI HITOSHI , BILOTTI ALBERTO
IPC分类号： G01D5/245 , G01D5/14 , G01P3/487 , G01P3/488 , G01P3/489 , G01R33/07

75. 发明专利

CA2562989A1 MAGNETIC POLE INSENSITIVE SWITCH CIRCUIT 未知
公开(公告)号：CA2562989A1
公开(公告)日：2000-03-30
申请号：CA2562989
申请日：1999-09-03
申请人： ALLEGRO MICROSYSTEMS INC
发明人： VIG RAVI , BILOTTI ALBERTO , FORREST GLENN A
IPC分类号： H01H36/00 , H04Q7/32
摘要： A switch which is magnetic pole insensitive is described. The switch include s a Hall effect sensor coupled to a threshold circuit which provides an output signal indicative of the proximity of magnet, and hence a magnetic field, to the Ha ll effect sensor regardless of the orientation of the magnet to the Hall effect sensor .

76. 发明专利

CA2562985A1 MAGNETIC POLE INSENSITIVE SWITCH CIRCUIT 未知
公开(公告)号：CA2562985A1
公开(公告)日：2000-03-30
申请号：CA2562985
申请日：1999-09-03
申请人： ALLEGRO MICROSYSTEMS INC
发明人： FORREST GLENN A , VIG RAVI , BILOTTI ALBERTO
IPC分类号： H01H36/00 , H04Q7/32
摘要： A switch which is magnetic pole insensitive is described. The switch include s a Hall effect sensor coupled to a threshold circuit which provides an output signal indicative of the proximity of magnet, and hence a magnetic field, to the Ha ll effect sensor regardless of the orientation of the magnet to the Hall effect sensor .

77. 发明专利

CA2343409A1 MAGNETIC POLE INSENSITIVE SWITCH CIRCUIT 未知
公开(公告)号：CA2343409A1
公开(公告)日：2000-03-30
申请号：CA2343409
申请日：1999-09-03
申请人： ALLEGRO MICROSYSTEMS INC
发明人： BILOTTI ALBERTO , FORREST GLENN A , VIG RAVI
IPC分类号： H01H36/00 , H03K17/90 , H03K17/945 , H03K17/95 , H03K17/97 , H04B1/40 , H04M1/00 , H04M1/02
摘要： A switch which is magnetic pole insensitive is described. The switch include s a Hall effect sensor coupled to a threshold circuit which provides an output signal indicative of the proximity of a magnet, and hence a magnetic field, to the Hall effect sensor regardless of the orientation of the magnet to the Ha ll effect sensor.

78. 发明专利

FR2742225B1 未知
公开(公告)号：FR2742225B1
公开(公告)日：1999-08-27
申请号：FR9615018
申请日：1996-12-06
申请人： ALLEGRO MICROSYSTEMS INC
发明人： BILOTTI ALBERTO , MONREAL GERARDO
IPC分类号： G01R15/20 , G01D5/14 , G01R33/07 , G11C27/02 , H01L43/06 , G01D5/12
摘要： A chopped Hall sensor includes a Hall-element switching circuit of the kind in which a Hall element has two pairs of diagonally opposite Hall contacts which are alternately connected to a pair of DC supply conductors and to a pair of Hall-stitching-circuit output conductors for alternately, during phase phi 1 and n phi 1 of a first clock signal, switching the Hall exciting current from flow in one to another direction through the Hall element. A linear analog double-differential Hall-voltage amplifier has an input connected to the output of the Hall switching-circuit. A sample-and-hold circuit is comprised of first and second elemental sample-and-hold circuits (ESHCs) with inputs connected respectively to the two Hall-voltage differential-amplifier outputs. The first and second ESHCs are respectively clocked, by second and third clock signals, to the sample Hall voltage signal only during phases phi 2 and phi 3 and to hold the sample signal during phases n phi 2 and n phi 3 respectively, where phi 2 and phi 3 occur respectively during a mid portion of phases phi 1 and n phi 1. Two inputs of a summer circuit are connected respectively to the outputs of the first and second ESHCs. A third and fourth ESHC may be added to form a crossed-polarity full-differential sample-and-hold circuit. The Hall voltage amplifier may include a clocked noise blanking circuit for reducing the differential-gain of the amplifier only during a time span encompassing each phase transition in the first clock signal.

79. 发明专利

DE19701260A1 未知
公开(公告)号：DE19701260A1
公开(公告)日：1997-07-24
申请号：DE19701260
申请日：1997-01-17
申请人： ALLEGRO MICROSYSTEMS INC
发明人： MOODY KRISTANN L , VIG RAVI , SCHELLER P KARL , TOWNE JAY M , TU TERI L
IPC分类号： G01B7/00 , G01D3/02 , G01D5/14 , G01D5/244 , G01D5/245 , G01V3/08 , H03K17/95 , H03M1/30 , G01P3/487 , G01R33/07
摘要： A Hall transducer produces a signal Vsig. Threshold voltages VPth and VNth are generated at the beginning, tupdate, of each of a succession of update time intervals, of 64 pulses in Vsig, to be fixed percentages respectively of the peak to peak voltage in Vsig. A proximity-detector binary output voltage is high when Vsig exceeds threshold voltage VPth and low when Vsig is below threshold voltage VNth. Signals VPold and VNold, generated by first and second DACs, are equal to the first positive and negative peaks in Vsig after each time tupdate initiating the start of a successive interval. Signals VPnew and VNnew, simultaneously generated by third and fourth DACs, are equal to the greatest positive and negative peak voltages in Vsig during the interval ending at tupdate. Counters present their count to the first and second DACs that count pulses from a clock for tracking and holding +/- peaks in Vsig. After each time tupdate, a pulse in a signal Vupdt is generated if at time tupdate VNnew lies outside the range. VNold-+Z v to VNold++Z v of if VNnew lies outside the range VNold-+Z v to VNold++Z v, where +Z v is an incremental DC bias voltage. Vupdt resets the counters so that during the succeeding update time interval the threshold voltages VPth and VNth have the fixed percentages of the updated threshold voltages VPnew-VNnew.

80. 发明专利

GB2309310A Detection of passing magnetic articles at speeds down to zero 未知
公开(公告)号：GB2309310A
公开(公告)日：1997-07-23
申请号：GB9700984
申请日：1997-01-17
申请人： ALLEGRO MICROSYSTEMS INC
发明人： TU TERI L , MOODY KRISTANN L , VIG RAVI , TOWNE JAY M
IPC分类号： G01B7/00 , G01D5/14 , G01D5/244 , G01D5/245 , G01V3/08 , H03K17/95
摘要： In a proximity-detector, a Hall transducer produces a signal Vsig. Two counters, P-counter and N-counter count pulses from a clock and produce count signals respectively to two DACs, PDAC and NDAC. The DACs output signals track and hold, respectively, the positive pulses and negative pulses in Vsig. These output signals are compared with Vsig to produce a proximity-detector binary output voltage Vout that becomes high when a tracking voltage VDAC-P produced by PDAC rises to each peak positive voltage Vpk in Vsig, and that becomes low when a tracking voltage VDAC-P falls to each peak negative voltage in Vsig. The peak VDAC-P is held until Vsig drops by a fixed amount below Vpk to produce an output pulse that resets the counter connected to PDAC at a time shortly following the actual peak in Vsig. Similarly, the peak VDAC-N is held until Vsig rises a fixed amount above VDAC-N to produce an output pulse that resets the counter connected to NDAC. The N-counter is reset at tnpk by the negative-peak indicating signal VNcomp and is enabled at tppk by the positive-peak indicating signal VPcomp, while the P-counter reset by the positive peak indicating signal VPcomp and enabled by VNcomp. This proximity detector detects articles passing at rates down to zero.

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