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71. 发明授权

US06873365B1 Timing generator of image input device 有权
标题翻译：图像输入装置的定时发生器
公开(公告)号：US06873365B1
公开(公告)日：2005-03-29
申请号：US09488712
申请日：2000-01-21
申请人： Gen Sasaki
发明人： Gen Sasaki
IPC分类号： H04N5/335 , H04N5/341 , H04N5/372 , H04N5/376 , H04N5/378 , H04N3/14
CPC分类号： H04N5/3765
摘要： Any complicates pulse waveform required depending on the type of CCD, can be generated with a simple circuit configuration. Specifically, any complicated pulse is obtainable by inputting an unlimited number of toggle timings, with no limitation imposed on the number of toggle timings inputted. This is achieved only by inputting different toggle timings sequentially from the exterior, because the toggle timing of toggle circuits (14 to 16) is regulated by shift registers (12a, 12b) of a loop structure and comparators (11a, 11b) connected to the rearmost stage of their respective shift registers (12a, 12b).
摘要翻译：根据CCD的类型需要复杂的脉冲波形，可以用简单的电路配置生成。具体而言，通过输入无限数量的切换定时可以获得任何复杂的脉冲，对输入的切换定时的数量没有限制。这仅通过从外部顺序地输入不同的切换定时来实现，因为切换电路（14至16）的触发定时由环路结构的移位寄存器（12a，12b）调节，并且比较器（11a，11b）被连接到它们各自的移位寄存器（12a，12b）的最后级。

72. 发明申请

US20050008230A1 Image processing apparatus 审中-公开
标题翻译：图像处理装置
公开(公告)号：US20050008230A1
公开(公告)日：2005-01-13
申请号：US10811840
申请日：2004-03-30
申请人： Gen Sasaki
发明人： Gen Sasaki
IPC分类号： G06T9/00 , H04N1/21 , H04N5/225 , H04N5/907 , H04N5/91 , H04N5/92 , H04N101/00 , H04N5/21
CPC分类号： G06T1/60 , H04N1/2112 , H04N1/2137 , H04N1/32491 , H04N5/772 , H04N2101/00 , H04N2201/3292
摘要： Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption.
摘要翻译：在图像处理单元和用于压缩成预定格式的图像压缩和扩展单元之间提供两个本地缓冲器。写和读控制单元用于交替使用两个本地缓冲区。结果，从图像处理单元开始，通过图像压缩和扩展单元生成压缩图像数据的处理流程不需要主存储器，由此以低功耗允许高速图像处理。

73. 发明申请

US20030160885A1 AF evaluation value calculating device 有权
标题翻译： AF评估值计算装置
公开(公告)号：US20030160885A1
公开(公告)日：2003-08-28
申请号：US10364378
申请日：2003-02-12
申请人： MEGA CHIPS CORPORATION
发明人： Gen Sasaki
IPC分类号： H04N005/232
CPC分类号： H04N5/23212
摘要： The present invention provides an AF evaluation value calculating device in which speed of AF control does not deteriorate even when a number of AF areas are set. The AF evaluation value calculating device for calculating an AF evaluation value used for AF (auto-focus) control of a digital camera, includes: at least one AF evaluation value calculating unit 13 for calculating an AF evaluation value in each of a plurality of AF areas which are set in an image area of image data supplied; and a data transmitter (17a and ch0) for transmitting the AF evaluation value calculated by the AF evaluation value calculator 13 into a predetermined memory by DMA (Direct Memory Access).
摘要翻译：本发明提供一种AF评价值计算装置，其中AF控制的速度即使设置了AF区域的数量也不会劣化。用于计算用于数字照相机的AF（自动对焦）控制的AF评估值的AF评估值计算装置包括：至少一个AF评估值计算单元13，用于计算多个AF中的每一个中的AF评估值设置在提供的图像数据的图像区域中的区域; 以及用于通过DMA（直接存储器访问）将由AF评估值计算器13计算出的AF评估值发送到预定存储器的数据发送器（17a和ch0）。

74. 发明申请

US20030156205A1 Hybrid pixel interpolating apparatus and hybrid pixel interpolating method 有权
标题翻译：混合像素内插装置和混合像素插值方法
公开(公告)号：US20030156205A1
公开(公告)日：2003-08-21
申请号：US10364381
申请日：2003-02-12
申请人： MEGA CHIPS CORPORATION
发明人： Gen Sasaki , Takashi Matsutani
IPC分类号： H04N005/225
CPC分类号： H04N9/045 , H04N2209/046
摘要： A hybrid pixel interpolating apparatus (1) has a function of converting raw image data (D1) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus (1) includes: a register (2) for holding pixel data in a predetermined pixel region in the raw image data (D1) to be inputted; a plurality of pixel interpolating parts (41, 42, . . . , 4nnull1, 4n (n: integer not less than 2)) for sampling pixel data (D2) inputted from the register (2) to execute a pixel interpolating process; and a mixing coefficient calculating part (3) for calculating mixing coefficients (null1, null2, . . . , nulln), and also includes a mixing part (5) for fetching and mixing interpolated data (DI1, DI2, . . . , DIn) outputted from the respective pixel interpolating parts (41 to 4n) to output the resultant. In the mixing coefficient calculating part (3), the mixing coefficients (null1 to nulln) are calculated for each of the pixel interpolating parts (41 to 4n) so as to suppress the deterioration in image quality at minimum.
摘要翻译：混合像素内插装置（1）具有将每个像素具有一个颜色分量的原始图像数据（D1）转换为每个像素具有多个颜色分量的像素内插数据的功能。该混合像素内插装置（1）包括：用于保存要输入的原始图像数据（D1）中的预定像素区域中的像素数据的寄存器（2）用于从寄存器（2）输入的用于采样像素数据（D2）的多个像素内插部分（41,42，...，4n-1,4n（n：整数，不小于2）），以执行像素内插处理 ; 和混合系数计算部分（3），用于计算混合系数（alpha1，alpha2，...，alphan），并且还包括用于取出和混合内插数据（DI1，DI2，...，DIn ）从各像素内插部（41〜4n）输出，输出。在混合系数计算部分（3）中，为每个像素内插部分（41至4n）计算混合系数（α1至α1），以便最小化图像质量的劣化。

75. 发明申请

US20030043290A1 AF control apparatus and AF control method 有权
标题翻译： AF控制装置和AF控制方法
公开(公告)号：US20030043290A1
公开(公告)日：2003-03-06
申请号：US10228918
申请日：2002-08-28
申请人： MEGA CHIPS CORPORATION
发明人： Gen Sasaki
IPC分类号： H04N005/232
CPC分类号： H04N5/23212 , H04N5/2256
摘要： nullPurposenull To reduce a focusing time. nullSolutionnull A CPU performs a control for photographing a main subject in absence of auxiliary light, whereby an image signal PSA is outputted from an analogue signal processing section. Next, the CPU performs a control for photographing the main subject in presence of the auxiliary light, whereby an image signal PSB is outputted from the analogue signal processing section. An AF area extracting section extracts image signals PSa, PSb in an AF area from the image signals PSA, PSB. A differential signal calculating section outputs a differential signal null1 between the image signal PSa, PSb, and a distance measuring section compares magnitudes of that differential signal null1 and a reference value in a distance data base to calculate distance information D1 based on the comparison result. An AF control section executes AF control of mountain climbing system with the use of the distance information D1.
摘要翻译： [目的]减少聚焦时间。 [解决方案] CPU在没有辅助光的情况下执行拍摄主要被摄体的控制，从而从模拟信号处理部分输出图像信号PSA。接下来，CPU在辅助光的存在下执行拍摄主被摄体的控制，由此从模拟信号处理部输出图像信号PSB。 AF区域提取部分从图像信号PSA，PSB中提取AF区域中的图像信号PSa，PSb。差分信号计算部分在图像信号PSa，PSb和距离测量部分之间输出差分信号DELTA1，其将距离数据库中的差分信号DELTA1的大小与参考值进行比较，以基于比较结果计算距离信息D1。 AF控制部使用距离信息D1执行登山系统的AF控制。

76. 发明授权

US5825083A Semiconductor device 失效
公开(公告)号：US5825083A
公开(公告)日：1998-10-20
申请号：US897414
申请日：1997-07-21
申请人： Akira Takata , Tetsuo Hikawa , Takashi Sawada , Tom Dang-hsing Yiu , Ful-Long Ni
发明人： Akira Takata , Tetsuo Hikawa , Takashi Sawada , Tom Dang-hsing Yiu , Ful-Long Ni
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/485 , H01L23/50 , H01L27/10 , H01L23/52
CPC分类号： H01L24/06 , H01L23/50 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/45124 , H01L2224/48247 , H01L2224/48699 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01082 , H01L2924/13091 , H01L2924/3011
摘要： In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

77. 发明授权

US5700975A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5700975A
公开(公告)日：1997-12-23
申请号：US411982
申请日：1995-03-28
申请人： Akira Takata , Tetsuo Hikawa , Takashi Sawada , Tom Dang-hsing Yiu , Ful-Long Ni
发明人： Akira Takata , Tetsuo Hikawa , Takashi Sawada , Tom Dang-hsing Yiu , Ful-Long Ni
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/485 , H01L23/50 , H01L27/10 , H01L23/02
CPC分类号： H01L24/06 , H01L23/50 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/45124 , H01L2224/48247 , H01L2224/48699 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01082 , H01L2924/13091 , H01L2924/3011
摘要： In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
摘要翻译：为了减少半导体器件的芯片尺寸以及在具有不同功能的至少两种类型的焊盘之间分离噪声，在封装（101）的相对边缘上提供至少一个Vcc和至少一个Vss，使得输出引脚或I / O引脚布置在其间，输入引脚布置在其外部。不连接的多余引脚（NC）布置在上边界和下边界，用于省略导线并减小芯片尺寸。

78. 发明授权

US5541505A Testing integrated circuits by consolidating a plurality of digital signals as a multilevel signal 失效
标题翻译：通过将多个数字信号合并为多电平信号来测试集成电路
公开(公告)号：US5541505A
公开(公告)日：1996-07-30
申请号：US121102
申请日：1993-09-14
申请人： Hideo Azumai
发明人： Hideo Azumai
IPC分类号： G01R31/3185 , G06F11/22 , G01R31/00
CPC分类号： G01R31/318516 , G06F11/2273
摘要： An apparatus for testing a semiconductor integrated circuit includes a plurality of probe lines and a plurality of sense lines which intersect each other to thereby define a plurality of intersections thereby as electrically isolated from each other. An electronic switch device is provided for each intersection for producing a multilevel signal, on an associated sense line, having one of a predetermined number of voltage levels corresponding to various combinations definable by a predetermined number of binary numbers supplied to test points from logic elements to be tested.In a four test point embodiment, four test points are arranged such that each test point is located in a corresponding one of four quadrants defined by a pair of probe and sense lines intersecting each other. Preferably, the integrated circuit is in the form of a gate array.
摘要翻译：一种用于测试半导体集成电路的装置包括多个探针线和多条彼此相交的感测线，从而限定多个交叉点，从而彼此电隔离。提供电子开关装置，用于在相关的感测线上产生多电平信号的多路交叉信号，该电平开关装置具有预定数量的电压电平中的一个电压电平，该电压电平对应于由逻辑元件提供给测试点的预定数量的二进制数可定义的各种组合被测试。在四个测试点实施例中，布置四个测试点，使得每个测试点位于由彼此相交的一对探针和感测线限定的四个象限中的对应的一个中。优选地，集成电路是门阵列的形式。

79. 发明授权

US5526306A Semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5526306A
公开(公告)日：1996-06-11
申请号：US255947
申请日：1994-06-07
申请人： Tetsuo Hikawa , Akira Takata , Takashi Sawada
发明人： Tetsuo Hikawa , Akira Takata , Takashi Sawada
IPC分类号： G11C17/12 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , G11C11/34
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5692 , G11C16/0483 , H01L27/112 , H01L27/11266 , G11C19/00 , G11C8/04
摘要： In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming several of types of memory cells having different electrical properties. Storage data per memory cell is therefore so multivalued that the number of memory cells is reduced.
摘要翻译：为了提高存储数据整合的程度，在字线（22）的侧面选择性地形成侧壁（32），以用作通过改变有源区的宽度或长度来改变存储单元的导通状态电流值的掩模（24），从而形成具有不同电特性的几种类型的存储单元。因此，每个存储器单元的存储数据是多值的，使得存储器单元的数量减少。

80. 发明申请

US20110150350A1 ENCODER AND IMAGE CONVERSION APPARATUS 有权
标题翻译：编码器和图像转换装置
公开(公告)号：US20110150350A1
公开(公告)日：2011-06-23
申请号：US12967790
申请日：2010-12-14
申请人： Makoto SAITOH , Yuki Haraguchi
发明人： Makoto SAITOH , Yuki Haraguchi
IPC分类号： G06K9/36
CPC分类号： H04N19/40 , H04N19/107 , H04N19/109 , H04N19/11 , H04N19/146 , H04N19/176 , H04N19/61
摘要： It is an object to provide a method of calculating a coding cost by which the magnitude relation of the amounts of generated codes can be estimated with high accuracy. A cost calculation part generates a differential block between a coding object block and a prediction block. Hadamard Transform is performed on the differential block to generate a frequency component block. A conversion factor matrix is generated with the information of a quantization matrix reflected thereon. A coding cost is calculated by multiplying components in the frequency component block individually by components in the conversion factor matrix and adding up the multiplied components. A mode selection part selects an optimum predictive coding method on the basis of the coding cost.
摘要翻译：本发明的目的是提供一种计算编码成本的方法，通过该方法可以高精度地估计生成的代码量的大小关系。成本计算部分在编码对象块和预测块之间生成差分块。在差分块上执行Hadamard变换以产生频率分量块。利用其上反映的量化矩阵的信息生成转换因子矩阵。通过将频率分量块中的分量分别乘以转换因子矩阵中的分量并相加乘法分量来计算编码成本。模式选择部分基于编码成本来选择最佳预测编码方法。

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