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61. 发明专利

JP3402680B2 失效
公开(公告)号：JP3402680B2
公开(公告)日：2003-05-06
申请号：JP21691193
申请日：1993-08-10
IPC分类号： H04B14/04 , H03M13/27 , H03M13/33 , H04L7/00
摘要： An interleaver (34) processes information in a pseudorandom order to provide pseudorandom interleaved data for communication to a deinterleaver (42). The pseudorandom interleaved data is processed at the deinterleaver (42) in a pseudorandom order corresponding to that used at the interleaver (34) means, to recover the original information. The pseudorandom processing at the deinterleaver is synchronized with the pseudorandom processing at the interleaver on a trial and error basis. In one embodiment, full synchronization occurs when a Viterbi decoder (44) receiving data from the deinterleaver has a renormalization rate within a designated threshold and when enough synchronization words are detected in data output from the deinterleaver to meet a predetermined criterion. In another embodiment, a timer is used to initiate a new starting address for the pseudorandom processing at the deinterleaver during successive time intervals. Synchronization is achieved when a start address is found that results in the detection of enough synchronization words in data output from the deinterleaver to meet a predetermined synchronization criterion.

62. 发明专利

JP3344934B2 失效
公开(公告)号：JP3344934B2
公开(公告)日：2002-11-18
申请号：JP28563597
申请日：1997-10-17
IPC分类号： H03M13/19 , H03M13/33 , H04L7/00 , H04L7/04 , H04L7/08 , H04L12/70 , H04N19/00 , H04N19/102 , H04N19/184 , H04N19/189 , H04N19/196 , H04N19/44 , H04N19/46 , H04N19/65 , H04N19/70 , H04N19/89 , H04L12/56 , H04N7/24

63. 发明专利

JP3309278B2 失效
公开(公告)号：JP3309278B2
公开(公告)日：2002-07-29
申请号：JP32213199
申请日：1999-11-12
IPC分类号： H04N19/102 , H03M13/13 , H03M13/27 , H03M13/33 , H03M13/41 , H04N7/24 , H04N19/00 , H04N19/134 , H04N19/196 , H04N19/44 , H04N19/46 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/88 , H04N19/89

64. 发明专利

JP3306823B2 失效
公开(公告)号：JP3306823B2
公开(公告)日：2002-07-24
申请号：JP20128099
申请日：1999-07-15
IPC分类号： H04N19/503 , H03M13/33 , H04J3/00 , H04L7/08 , H04N7/24 , H04N19/00 , H04N19/61 , H04N19/625 , H04N19/65 , H04N19/70 , H04N19/85

65. 发明专利

JP2001177421A VITERBI DECODER AND SYNCHRONIZATION CONTROL METHOD 失效
公开(公告)号：JP2001177421A
公开(公告)日：2001-06-29
申请号：JP35726999
申请日：1999-12-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： HORI MITSURU , MACHIDA HIROHISA
IPC分类号： H03M13/33 , H03M13/23 , H03M13/41 , H04L7/00 , H04L27/00
摘要： PROBLEM TO BE SOLVED: To properly and easily set a threshold value in response to a set measurement time. SOLUTION: The Viterbi decoder is provided with a decoding means consisting of a Viterbi decoding section 3 decoding received data, a coding means consisting of a convolution coder 4 coding decoded data resulting from decoding the received data by the decoding means, for detecting a bit error correction number for a measurement period set externally from an output of the coding means, and for detecting a synchronization state on the basis of the detected bit error correction number and a threshold value, a threshold value detection means consisting of a threshold value detection circuit 8 that detects the threshold value from the bit error correction number detected for the threshold value detection period including a measurement period set externally as to the output of the coding means.

66. 发明专利

JP2001148689A CODE SYNCHRONOUS CIRCUIT 失效
公开(公告)号：JP2001148689A
公开(公告)日：2001-05-29
申请号：JP32970099
申请日：1999-11-19
申请人： NEC CORP , NIPPON ELECTRIC ENG
发明人： KUROGAMI YUUZOU , SATO HIROTAKA
IPC分类号： H03M13/15 , H03M13/33 , H04L1/00 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To shorten the code synchronizing time without enlarging the circuit scale of parallel processing. SOLUTION: This code synchronous circuit establishing the code synchronization of code words using the cyclic codes, is provided with a zero detection circuit 11 which decides a dividing line of code words from a position where the coefficient of a remainder syndrome polynomial where a receiving data string is divided by a generator polynomial is equal to zero and a syndrome sequential calculation circuit 10 which calculates in sequence the coefficients of syndrome polynomials concerning a receiving polynomial that elapsed by one clock to an instantaneous receiving polynomial of a clock (t) at every time when a bit of a data string is inputted.

67. 发明专利

JP3135786B2 失效
公开(公告)号：JP3135786B2
公开(公告)日：2001-02-19
申请号：JP9421594
申请日：1994-05-06
IPC分类号： H04L1/00 , H03M13/33 , H04B14/00 , H04J3/06 , H04L7/08

68. 发明专利

JP2001036515A SYNCHRONIZATION DETECTOR AND DECODER 失效
公开(公告)号：JP2001036515A
公开(公告)日：2001-02-09
申请号：JP20128099
申请日：1999-07-15
申请人： YRP MOBILE TELECOMMUNICATIONS KEY TECH RES LAB CO LTD , TOSHIBA CORP
发明人： YAMAZAKI SHOICHIRO
IPC分类号： H04N19/503 , H03M13/33 , H04J3/00 , H04L7/08 , H04N7/24 , H04N19/00 , H04N19/61 , H04N19/625 , H04N19/65 , H04N19/70 , H04N19/85
摘要： PROBLEM TO BE SOLVED: To enhance a detection characteristic and an error correction characteristic of a synchronizing signal. SOLUTION: A communication path coder 1 generates a check signal stream CHK from an information signal stream INF at a transmitter side, which transmits both the signal streams INF and CHK. A receiver side uses a communication path decoder 2 to decode the received INF and outputs a decoded INF and a decoded CHK. The decoded CHK includes a check signal stream corresponding to a synchronizing signal SYNC (synchronization flag). A data extract section 3 extracts the decoded INF stream and a correlation arithmetic section 4 obtains a correlation value with respect to a code pattern corresponding to the synchronizing signal SYNC. A data extract section 5 extracts the decoded CHK and a correlation arithmetic section 6 calculates a correlation value with the code pattern of the check signal stream corresponding to the SYNC. The synchronizing signal SYNC is detected by outputs from both the correlation arithmetic sections 4, 6.

69. 发明专利

JP3118233B2 失效
公开(公告)号：JP3118233B2
公开(公告)日：2000-12-18
申请号：JP32036299
申请日：1999-11-10
IPC分类号： H04N19/102 , H03M7/40 , H03M13/33 , H04N7/24 , H04N19/00 , H04N19/166 , H04N19/172 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/85 , H04N19/89

70. 发明专利

JP2000188754A METHOD FOR CODING/DECODING MOVING PICTURE SIGNAL AND CODER/DECODER 失效
公开(公告)号：JP2000188754A
公开(公告)日：2000-07-04
申请号：JP32036299
申请日：1999-11-10
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MACHIDA YUTAKA
IPC分类号： H04N19/102 , H03M7/40 , H03M13/33 , H04N7/24 , H04N19/00 , H04N19/166 , H04N19/172 , H04N19/65 , H04N19/67 , H04N19/70 , H04N19/85 , H04N19/89
摘要： PROBLEM TO BE SOLVED: To realize a coding/decoding method for a digital moving picture signal where synchronization setup by a false synchronous word or out of synchronism due to a bit error in a synchronous word can be suppressed even on the occurrence of the bit error in a bit stream consisting of coded moving picture signals. SOLUTION: A bit number count means 103 counts number of bits of a variable length code stream for one picture and an error correction coding means 104 applies error correction coding to a block code on the basis of the run length information. A frame configuration 105 adds the block code to a head of the variable length code stream for one picture and a synchronous word addition means 106 adds a synchronous word before the block code. A decoder side applies error correction decoding to the block code, and suppresses setup of synchronization by a false synchronous word when there is any error and sets up synchronization by discriminating the synchronous word to be correct when there is no error.

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